• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.304-308
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• 2003

A low cost solution employing harmonic oscillation to the frequency synthesizer at 5.8 GHz is proposed. The proposed frequency synthesizer is composed of 2.9GHz PLL chip, 2.9GHz oscillator, and 5.8GHz buffer amplifier. The measured data shows a frequency tuning range of 290MHz, ranging from 5.65 to 5.94GHz, about 0.5dBm of output power, and a phase noise of -107.67 dBc/Hz at the 100kHz offset frequency. All spurious signals including fundamental oscillation power (2.9GHz) are suppressed at least 15dBc than the desired second harmonic signal.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.224-228
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• 2003

In this paper, for phase lock loop(PLL) synthesizer, we introduce a novel but simple and low cost frequency modulation(FM) circuit of a flat peak frequency deviation for modulation signal from high to very low frequency penetrating into the loop-bandwidth of PLL. The FM circuit was basically designed to compensate an amount of feedback of the loop filter in PLL. The circuit also includes the capability of the adjustment of peak frequency deviation and blocking the interference with the loop filter. The designed circuit was successfully implemented and showed the flat frequency deviation as expected in the design.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.4
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• pp.421-427
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• 2004

A low cost solution employing harmonic oscillation to the frequency synthesizer at 5.8 ㎓ is proposed. The proposed frequency synthesizer is composed of 2.9 ㎓ PLL chip, 2.9 ㎓ oscillator, and 5.8 ㎓ buffer amplifier The measured data shows a frequency Outing range of 290 ㎒, ranging from 5.65 to 5.94 ㎓ about 0.5 ㏈m of output power, and a phase noise of -107.67 ㏈c/㎐ at the 100 ㎑ offset frequency. All spurious signals including fundamental oscillation power(2.9 ㎓) are suppressed at least 15 ㏈c than the desired second harmonic signal.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.37-40
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• 2003

The 1.63㎓, 2.33㎓ dual-band PLL frequency synthesizer has been developed for applications to the miniature repeater. The miniature dual-band repeater will be used at shopping mall, basements and underground parking lots. The in-loop 1.63㎓, 2.33㎓ dual-band PLL frequency synthesizer has been developed by designing Si BJT VCO and PLL loop circuits with Colpitts. The prototype of 1.63㎓, 2.33㎓ dual-band PLL frequency synthesizer of size 19${\times}$19${\times}$8(mm) has shown operating frequencies of 1.63㎓, 2.33㎓ ranges, RF output of 1dBm(PCS), 1dBm(IMT-2000), phase noise of -100 dBc/Hz(PCS), -95dBc/Hz(IMT-2000) at 10KHz offset, harmonics suppression of -24dB c(PCS), -15dBc(IMT-2000).

• Journal of the Korea Institute of Military Science and Technology
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• v.13 no.5
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• pp.775-784
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• 2010

In this paper we propose a design method of X band frequency hopping synthesizer in terms of phase noise and settling time with DDS driven PLL architecture, which has the advantages of high frequency resolution, fast settling time and small size. In addition, a noble method is proposed to remove the synthesizer output spurious signals due to superposition effect of DDS. The spurious signal which depend on its normalized frequency of DDS, can be dominant if they occur within the PLL loop bandwidth. We verify that the sources of that spurious signals are quasi-amplitude modulation and superposition effect, and suggest that such signals can be eliminated by intentionally creating frequency errors in the developed synthesizer.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.890-893
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• 2003

In this paper, we have designed the fractional-N frequency synthesizer for bluetooth system using 0.35-um CMOS technology and 3.3-V single power supply. The designed synthesizer consist of phase-frequency detector (PFD), charge pump, loop filter, voltage controlled oscillator (VCO), frequency divider, and sigma-delta modulator. A dead zone free PFD is used and a modified charge pump having active cascode transistors is used. A Multi-modulus prescaler having CML D flip-flop is used and VCO having a tuning range from 746 MHz to 2.632 GHz at 3.3 V power supply is used. Total power dissipation is 32 mW and phase noise is -118 dBc/Hz at 1 MHz offset.

• Journal of the Korea Safety Management & Science
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• v.17 no.3
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• pp.377-381
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• 2015

For the first time, PLL frequency synthesizer using DDS was adapted for the data link communication system which should fast transmit and receive each other with the correct information and fast Hopping System. It is inevitable to lost the synchronization by slow lock time about PLL and no cut off the noise. This paper propose the design of PLL frequency synthesizer which can make 800MHz frequency range. The PLL frequency synthesizer has three high qualities those are frequency accuracy, fast lock time and outstanding phase noise.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.11
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• pp.1272-1280
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• 2008

In this paper, we have proposed a phase noise model of fast frequency hopping synthesizer with DDS Driven PLL architecture. To accurately model the phase noise contribution of noise sources in frequency hopping synthesizer, they were investigated using model of digital divider for PLL, DAC for DDS and Leeson's model for reference oscillator and VCO. Especially it was proposed that the noise component of low pass filter was considered together with the phase noise of VCO. Under assuming linear operation of a phase locked loop, the phase noise transfer functions from noise sources to the output of synthesizer was analyzed by superposition theory. The proposed phase noise prediction model was evaluated and its results were compared with measured data.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.3
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• pp.9-14
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• 2020

In this paper, Qualification Model of frequency synthesizer is designed for X-band SAR system and performed electrical and environment test. Designed frequency synthesizer generate 13.65 GHz with very low phase noise performance. The integrated phase noise from 10Hz to 1MHz is -37.91 dBc. IRF performances are analyzed according to phase noise and jitter. Also, thermal and structure analysis are achieved for stable operation in space environment. Designed frequency synthesizer is consist of 2 modules of 6U size and generate L-band, C-band, Ku-band. The result of this study would enhance the design ability of RF module and help the frequency synthesizer design for SAR payload system.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.6
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• pp.51-57
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• 2017

In this paper, we designed a frequency synthesizer using DDS (Direct Digital Synthesizer) for Ka-band compact Radar. DDS is applied to generate various waveform and to cover high-speed frequency sweep. In order to reduce size, waveform generator and Ka band frequency up-converter are integrated in one module. Proposed frequency synthesizer provides LFM(Linear Frequency Modulation) waveform and Phase modulated FMCW (Frequency Modulation Continuous Wave) waveform. It is observed that fabricated synthesizer performs $0.191{\mu}sec$ frequency switching time and -89.16 dBc/Hz phase noise at offset 1 kHz.