• Journal of IKEEE
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• v.19 no.2
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• pp.265-270
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• 2015

In this paper, we proposed a dual-directional SCR (silicon-controlled rectifier) based ESD (electrostatic discharge) protection circuit. In comparison with conventional SCR, this ESD protection circuit can provide an effective protection against ESD pulses in the two opposite directions, so the ESD protection circuit can be discharged in two opposite direction. The proposed circuit has a higher holding voltage characteristic than conventional SCR. These characteristic enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. it was analyzed to figure out electrical characteristics in term of individual design parameters. They are investigated by using the Synopsys TCAD simulator. In the simulation results, it has trigger voltage of 6.5V and holding voltage increased with different design parameters. The holding voltage of the proposed circuit changes from 2.1V to 6.3V and the proposed circuit has symmetrical I-V characteristic for positive and negative ESD pulse.

• Journal of IKEEE
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• v.17 no.2
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• pp.208-213
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• 2013

In this paper, we proposed the novel SCR-based ESD protection circuit with high holding voltage for power clamp. In order to increase the holding voltage, the floating p+ and n+ to n-well and p-well, respectively, in the conventional SCR. The resulting increase of the holding voltage of the our proposed ESD circuit enables the high latch-up immunity. The electrical characteristics including ESD robustness of the proposed ESD circuit have been simulated using Synopsys TCAD simulator. According to the simulation result, the proposed device has higher holding voltage of 4.98 V than that of the conventional SCR protection circuit. Moreover, it is confirmed that the device could have the holding voltage of maximum 13.26 V with the size variation of floated diffusion area.

• Journal of IKEEE
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• v.24 no.4
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• pp.1156-1161
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• 2020

In this paper, we propose a new ESD protection circuit with improved electrical characteristics through structural changes of the existing one-way SCR. The proposed ESD protection circuit has high holding voltage characteristics due to the inserted N+ floating and P+ floating regions, and thus the latch-up immunity characteristics are improved. In addition, structural change enables ESD discharge in four types of Zapping mode (PD, PS, ND, NS), and has superior area efficiency than unidirectional SCR. In addition, the P+ floating and N+ floating lengths corresponding to the base length of the parasitic bipolar transistor, and the distance between P+ floating and N+ floating were designated as design variables, and the high holding voltage was verified through Synopsys' TCAD Simulator.

• Journal of IKEEE
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• v.25 no.2
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• pp.350-355
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• 2021

IGBT is a power semiconductor device that contains both MOSFET and BJT structures, and it has fast switching speed of MOSFET, high breakdown voltage and high current of BJT characteristics. IGBT is a device that targets the requirements of an ideal power semiconductor device with high breakdown voltage, low V_CE-SAT, fast switching speed and high reliability. In this paper, we analyzed Gate oxide thickness, Trench Gate Width, and P+Emitter width, which are the top process parameters of 1,200V Trench Gate Field Stop IGBT, and suggested the optimized top process parameters. Using the Synopsys T-CAD Simulator, we designed IGBT devices with electrical characteristics that has breakdown voltage of 1,470 V, V_CE-SAT 2.17 V, Eon 0.361 mJ and Eoff 1.152 mJ.

• Journal of IKEEE
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• v.25 no.2
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• pp.376-380
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• 2021

In this paper, we propose a novel ESD protection device with Latch-up immunity properties due to high holding voltages by improving the structure of a typical SCR. To verify the characteristics of the proposed ESD circuit, simulations were conducted using Synopsys TCAD and presented compared to existing ESD protection circuits. Furthermore, the variation of electrical properties was verified using the design variable D1. Simulation results confirm that the proposed ESD protective circuit has higher holding voltage properties and bidirectional discharge properties compared to conventional ESD protective circuits. We validate the electrical properties with post-design TLP measurements using Samsung's 0.13um BCD process. And we verify that the proposed ESD protection circuit in this paper is well suited for high voltage applications in that it has a latch-up immunity due to improved holding voltage through optimization of design variables.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.12
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• pp.702-708
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• 2020

Recently, as LED display systems have become larger, research on effective power control methods for the systems has been in progress. This paper proposes a power control method to minimize power loss due to the difference in LED characteristics for each channel of a backlight unit (BLU) system. The proposed LED driver IC has a power optimization function and detects the minimum headroom voltage for constant current operation of all channels and linearly controls the DC-DC converter output. Thus, it minimizes power consumption due to unnecessary additional voltage. In addition, it does not require a voltage sensing comparator or a voltage generation circuit for each channel. This has a great advantage in reducing the chip size and for stabilization when implementing an integrated circuit. In order to verify the proposed function, an IC was designed using Cadence and Synopsys' design tools, and it was fabricated with a Magnachip 0.35um 5V/40V CMOS process. The experiments confirmed that the proposed power control method controls the minimum required voltage of the BLU system.

• Journal of IKEEE
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• v.25 no.4
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• pp.735-740
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• 2021

In this paper, we propose a new ESD protection device with high holding voltage with low current gain of parasitic NPN BJT by improving the structure of the existing LTDDSCR. The electrical characteristics of the proposed protection device were analyzed by HBM simulation using Synopsys' TCAD simulation, and the operation of the added BJT was confirmed by current flow, impact ionization and recombination simulation. In addition, the holding voltage characteristics were optimized with the design variables D1 and D2. As a result of the simulation, it was verified that the new ESD protection device has a higher holding voltage compared to the existing LTDDSCR and has a symmetrical bidirectional characteristic. Therefore, the proposed ESD protection device has high area efficiency when applied to an IC and is expected to improve the reliability of the IC.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.4
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• pp.671-678
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• 2022

Approximate computing is an computational technique that is acceptable degree of inaccurate results of accurate results. Approximate multiplication is one of the approximate computing methods for high-performance and low-power computing. In this paper, we propose a high-density, low-power, and high-speed approximate multiplier using approximate 4-2 compressor and improved full adder. The approximate multiplier with approximate 4-2 compressor consists of three regions of the exact, approximate and constant correction regions, and we compared them by adjusting the size of region by applying an efficient partial product reduction. The proposed approximate multiplier was designed with Verilog HDL and was analyzed for area, power and delay time using Synopsys Design Compiler (DC) on a 25nm CMOS process. As a result of the experiment, the proposed multiplier reduced area by 10.47%, power by 26.11%, and delay time by 13% compared to the conventional approximate multiplier.

• Journal of Power Electronics
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• v.12 no.1
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• pp.19-23
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• 2012

This paper presents a practical methodology for realistic simulation on reverse characteristics of Wide Bandgap (WBG) SiC and GaN p-n junctions. The adjustment on certain physic-based model parameters, such as the trap density and photo-generation for SiC junction, and impact ionization coefficients and critical field for GaN junction are described. The adjusted parameters were used in Synopsys Medici simulation to obtain a realistic p-n junction avalanche breakdown voltage. The simulation results were verified through benchmarking against independent data reported by others.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.164-167
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• 2002

This paper presents the design of Rijndael crypto-processor with 128 bits, 192 bits and 256 bits key size. In October 2000 Rijndael cryptographic algorithm is selected as AES(Advanced Encryption Standard) by NIST(National Institute of Standards and Technology). Rijndael algorithm is strong in any known attacks. And it can be efficiently implemented in both hardware and software. We implement Rijndael algorithm in hardware, because hardware implementation gives more fast encryptioN/decryption speed and more physically secure. We implemented Rijndael algorithm for 128 bits, 192 bits and 256 bits key size with VHDL, synthesized with Synopsys, and simulated with ModelSim. This crypto-processor is implemented using on-the-fly key generation method and using lookup table for S-box/SI-box. And the order of Inverse Shift Row operation and Inverse Substitution operation is exchanged in decryption round operation of Rijndael algorithm. It brings about decrease of the total gate count. Crypto-processor implemented in these methods is applied to mobile systems and smart cards, because it has moderate gate count and high speed.