• The Transactions of the Korean Institute of Electrical Engineers P
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• v.66 no.4
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• pp.182-187
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• 2017

Synchronous generators have been significantly applied in large-scale power plants and its monitoring systems are additionally established to sequentially observe states and outputs. We develop a computer based monitoring device for three-phase synchronous power generators in this paper. First, a test-bed of such generator system is created and then a interface board is constructed to transfer electric signals including the output voltage and the current from generators into a computer system via a data acquisition device. Its RMS(root-mean-square) values are continuously shown on a screen of computer systems and its time-histories graphs are additionally illustrated under a graphic user interface(GUI) mode. Lastly, we carry out real-time experiments using the generator system with the monitoring device to demonstrate its reliability and superiority by comparing results of a generic power analyzer which is well-used in measuring various power systems practically.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.321-334
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• 2003

Globally-Asynchronous Locally-Synchronous (GALS) systems are worthy of notice as an adequate architecture for a large scaled chip design with guaranteeing easy designs and functional confidence. In this paper, we suggest an advanced structure of the interface unit which is indispensable for GALS systems by using stoppable clocks. The proposed interface unit is composed of a sender module and a receiver module. The sender module can carry out data transmission partially without the relation to an internal clock. We have designed it with 0.25${\mu}{\textrm}{m}$ standard cell library at the gate level and simulated its operation to show performance improvement. Finally, we constructed all example circuit with the interface unit and proved the correct operation of it.

• Journal of Internet Computing and Services
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• v.9 no.5
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• pp.185-193
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• 2008

An MTBF(mean time between failures) of large scale parallel systems is known to be only an order of several hours, and large computations sometimes result in a waste of huge amount of CPU time, However. the MPI(Message Passing Interface), a de facto standard for message passing parallel programming, suggests no possibility to handle such a problem. In this paper, we propose an application-level fault tolerant computation system, purely on the basis of the current MPI standard without using any non-standard fault tolerant MPI library, that can be used for general scientific synchronous parallel computation.

• Journal of Electrical Engineering and Technology
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• v.1 no.3
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• pp.313-319
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• 2006

This paper addresses improving the voltage stability limit of interface flow between two different regions in an electric power system using the Static Synchronous Series Compensator (SSSC). The paper presents a power flow analysis model of a SSSC, which is obtained from the injection model of a series voltage source inverter by adding the condition that the SSSC injection voltage is in quadrature with the current of the SSSC-installed transmission line. This model is implemented into the modified continuation power flow (MCPF) to investigate the effect of SSSCs on the interface flow. A methodology for determining the interface flow margin is simply briefed. As a case study, a 771-bus actual system is used to verify that SSSCs enhance the voltage stability limit of interface flow.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.3
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• pp.529-536
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• 2019

In order to apply a piezoelectric energy harvester to a smart sensor system, an energy harvest interface circuit including an AC-DC rectifier is required. In this paper, we compared the performance of full bridge rectifier, which is a typical energy harvester interface circuit, and synchronous piezoelectric energy harvest interface circuit by using board-level simulation. As a result, the output power of a synchronous electric charge extraction(: SECE) circuit is about four times larger than that of the full bridge rectifier, and there is little load variation. And a high voltage comparator, which is essential for the SECE circuit for the piezoelectric energy harvester with an output voltage of 40V or more, was designed using 0.35 um BCD process. The SECE circuit using the designed high-voltage comparator proved that the output power is 427 % higher than the FBR circuit.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.349-352
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• 2001

As microprocessor and SOC (System On a Chip) performance moves into the GHz speed, the high-speed asynchronous design is becoming challenge due to the disadvantageous power and speed aspects in synchronous designs. The next generation on-chip systems will consist of multiple independently synchronous modules and asynchronous modules for higher performance, so the interface module for data transfer between multiple clocked IPs is designed with Xilinx FPGA and simulated with RISC microprocessor.

• Journal of Electrical Engineering and Technology
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• v.10 no.3
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• pp.812-819
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• 2015

This paper presents a new approach for simulating the internal faults of synchronous machines using distributed computing and Large Change Sensitivity (LCS) analysis. LCS analysis caters for a parallel solution of 3-phase model of a faulted machine within the symmetrical component-based model of interconnected network. The proposed method considers dynamic behavior of the faulty machine and connected system and tries to accurately solve the synchronous machine’s internal fault conditions in the system. The proposed method is implemented in stand-alone FORTRAN-based phasor software and the results have been compared with available recordings from real networks and precisely simulated faults by use of the ATP/EMTP as a time domain software package. An encouraging correlation between the simulation results using proposed method, ATP simulation and measurements was observed and reported. The simplified approach also enables engineers to quickly investigate their particular cases with a reasonable precision.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.783-786
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• 1998

We designed a 3.3 V, 400 Mbps IEEE-1394 physical layer transeiver on 0.6um 1P3M CMOS process. The transceiver drives a twisted pair cable of which differential impedance is 110 $\Omega$ so that differential amplitude reaches 200 mV at 400 Mbps and restores this small signal to rail-to-rail. Also, the transceiver arbitrates the interface among nodes on a bus configuration and supports both synchronous interface and asynchronous interface.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.50-69
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• 2001

Three kinds of high-speed signaling methods for synchronous DRAM (SDRAM) bus interface channels (PC-133, Direct-Rambus, and SSTL-2) were analyzed in terms of the timing budget and the physical transmission characteristics. To analyze the SDRAM bus interface channels, loss mechanisms and the effective characteristic impedance method were reviewed and the ABCD matrix method was proposed as an analytic and yet accurate method. SPICE simulations were done to get the AC responses and the eye patterns of the three SDRAM bus interface channels for performance comparisons. Recent progress and future trend for SDRAM bus interface standards were reviewed.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.67-74
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• 2004

Most of today's parallel numerical schemes use synchronous algorithms, where some processors that have finished their tasks earlier than others must wait at synchronization points for correct computation. Hence overall performance of the system is dependent upon the speed of the slowest processor. In this paper, we det·ise a synchronous/asynchronous hybrid algorithm to accelerate convergence of the solution for finding the dominant eigenpair of a large matrix, by reducing the idle times of faster processors using MPMD programming methodology.