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Enhancement of Interface Flow Limit using Static Synchronous Series Compensators

  • Kim Seul-Ki (Power Conversion and System for RES Research Group, Korea Electro-technology Research Institute) ;
  • Song Hwa-Chang (Department of Electrical Engineering, Kunsan University) ;
  • Lee Byoung-Jun (Department of Electrical Engineering, Korea University) ;
  • Kwon Sae-Hyuk (Department of Electrical Engineering, Korea University)
  • Published : 2006.09.01

Abstract

This paper addresses improving the voltage stability limit of interface flow between two different regions in an electric power system using the Static Synchronous Series Compensator (SSSC). The paper presents a power flow analysis model of a SSSC, which is obtained from the injection model of a series voltage source inverter by adding the condition that the SSSC injection voltage is in quadrature with the current of the SSSC-installed transmission line. This model is implemented into the modified continuation power flow (MCPF) to investigate the effect of SSSCs on the interface flow. A methodology for determining the interface flow margin is simply briefed. As a case study, a 771-bus actual system is used to verify that SSSCs enhance the voltage stability limit of interface flow.

Keywords

References

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