• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.4A
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• pp.434-439
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• 2008

This paper proposes an efficient coarse frequency synchronizer for digital video broadcasting - second generation (DVB-S2). The input signal requirement of acquisition range for coarse frequency estimator in the DVB-S2 is around ${\pm}1.5625Mhz$, which corresponds to 6.25% of the symbol rate at 25Mbaud. At the process of analyzing the robust algorithm among data-aided approaches, we find that the Luise & Reggiannini (L&R) algorithm is the most promising one for coarse frequency estimation with respect to estimation performance and complexity. However, it requires many multipliers and adders to compute output values of correlators. We propose an efficient architecture identifying the serial correlator with the buffer and multiplexers. The proposed coarse frequency synchronizer can reduce the hardware complexity about 92% of the direct implementation. The proposed architecture has been implemented and verified on the Xilinx Virtex II FPGA.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.6
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• pp.1112-1121
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• 2011

A microgrid is an aggregation of multiple distributed generators (DGs) such as renewable energy sources, conventional generators, and energy storage systems that provide both electric power and thermal energy. Generally, a microgrid operates in parallel with the main grid. However, there are cases in which a microgrid operates in islanded mode, or in a disconnected state. Islanded microgrid can change its operational mode to grid-connected operation by reconnection to the grid, which is referred to as synchronization. Generally, a single machine simply synchronizes with the grid using a synchronizer. However, the synchronization of microgrid that operate with multiple DGs and loads cannot be controlled by a traditional synchronizer, but needs to control multiple generators and energy storage systems in a coordinated way. This is not a simple job, considering that a microgrid consists of various power electronics-based DGs as well as alternator-based generators that produce power together. This paper introduces the results of research examining an active synchronizing control system that consists of the network-based coordinated control of multiple DGs. Consequently, it provides the microgrid with a deterministic and reliable reconnection to the grid. The proposed method is verified by using the test cases with the experimental setup of a microgrid pilot plant.

• Proceedings of the IEEK Conference
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• summer
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• pp.77-81
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• 2004

In this paper, we propose a analog front-end (AFE) for noncoherent On-Off Keying (OOK) Ultra Wide Band (UWB) system based on power detection. The proposed AFE are designed using 0.18 micron CMOS technology and verified by simulation using SPICE. The proposed AFE consist of Sample-and-Hold block, Analog-to-Digital converter, synchronizer, delayed clock generator and impulse generator. The time resolution of 1ns is obtained with 100MHz system clocks and the synchronized 10-bit digital outputs are delivered to the baseband. The impulse generator produces 1ns width pulse using digital CMOS gates. The simulation results show the feasibility of the proposed UWB AFE systems.

• ETRI Journal
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• v.9 no.2
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• pp.96-105
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• 1987

The purpose of this paper is to report the implementation of new frame synchroniazation circuit for D3/PCM.When the D3/PCM signal(1.544Mb/s) is received, the performance of the new frame synchronizer is evaluated by the statistical method according to the parameters BER,es, em. For BER=$10^-2$, es=0 and em=2, the implemented hardware will render the initial search time, the maintenance time and there frame time equals to 2.87ms, 9.9hrs and2.69ms, respectively. Also the proposed frame synchronizer can be easily modified to the practical transmission channels environment and the new 1.544Mb/s signal format.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1C
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• pp.40-44
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• 2010

The timing error detector(TED) employed in the closed loop type timing synchronization scheme for an MQASK all digital receiver suffers from the selfnoise-induced timing jitter. To eliminate the timing jitter a prefilter can be added in front of the TED. The prefilter method, however, degrades the stability and timing acquisition performance due to the loop delay and increases the complexity of the synchronizer. This paper proposes a polyphase filter type resampler approach to optimize the performance and architecture of the synchronizer simultaneously. The proposed scheme uses two resamplers which performs matched filtering and matched prefiltering so that the loop delay is minimized with minimal hardware resources. Simulation results showed an excellent acquisition performance with reduced timing jitter.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1033-1036
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• 1998

본 논문은 FLEX 디코더에서 필요한 심볼 클럭을 생성하기 위한 심볼 동기 알고리즘을 제안하고, 제안한 알고리즘을 기본으로 한 심볼을 동기회로의 설계에 관한 것이다. 제안한 알고리즘은 조-만 게이트 동기 (ELGS:Early-Late Gate Synchronization)기법을 이용하고 있다. VHDL(VHSIC Hardware Description Language)로 설계된 심볼 동기회로는 Synopsys 툴을 이용하여 기능레벨의 시뮬레이션을 수행하였고, Altera MAX+plus II를 이용하여 타이밍 분석을 수행하였다. 실험 결과로부터 Source unit와 FLEX 디스코더와의 시스템 동기가 정확히 이루어짐을 확인하였다.

• Proceedings of the Korea Society for Simulation Conference
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• 1998.03a
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• pp.38-42
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• 1998

본 논문에서는 DEVS 형식론과 High Level Architecture에 기반을 둔 이 기종 시뮬레이션 환경의 구축에 대해 기술한다. DEVS 형식론은 여러 가지 방법으로 기술된 모델들을 동일한 형식론으로 간주하기 위해 사용되었다. 즉, 이산사건 모델링을 위한 세가지 세계관(world view)으로 기술된 시뮬레이션 모델들을 DEVS 형식론으로의 변환을 통해 전체적으로는 DEVS 형식론만을 사용한 것과 동일한 형태로 표현되도록 하였다. High Level Architecture는 시뮬레이션 수행시의 상호 연동성을 보장하기 위해 사용되었다. 이때, DEVS 형식론과 High Level Architecture에서의 시뮬레이션 시간 진행 방법이 다르기 때문에 이의 해결을 Synchronizer, EOS 방법을 제안하였다.

• Proceedings of the Acoustical Society of Korea Conference
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• 1991.06a
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• pp.78-81
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• 1991

Digital radio data is composed of groups which are divided into 4 blocks of 26 bits. And each block is made up of information word and check word. Check word of digital radio data that is composed ofcode word and offset word is used for group/block synchronization and error correction. In this paper, we have investigated the group/block synchronizer using offext word and shortened cyclic decoder for correcting error produced during the radio data transimission. Also, we have simulated the decoding process of the proposed decoder. From the simulation results, we have confirmed that the proposed decoder most with the required coding capcbility.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.2A
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• pp.202-213
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• 2004

In this paper, we propose a preamble structure and synchronization/channel estimation methods for OFDM-based multiple antenna WLAN systems that have 200Mbps transmit rate. With the proposed preamble structure, multiple antenna WLAN systems are backward-compatible with IEEE 802.11a systems which use the same 5㎓ band and synchronization performance is better than that of single antenna OFDM systems. For channel estimation, the preamble overhead is small and performance degradation by timing synchronization error that causes the critical problem of conventional comb-type multiple antenna channel estimation method also can be minimized by frequency domain phase recovery. Synchronizer and channel estimator for proposed preamble structure are implemented and verified using Verilog HDL. For the system with 4 transmit antennas and 4 receive antennas, about 150K gates are needed for synchronizer and 12K gates for channel estimator.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.37 no.3
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• pp.373-378
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• 2013

The speed change performance of transmissions has become a serious issue because of the increase in the inertia moment that has accompanied increases in engine output and transmission size. Therefore, it is necessary to develop better wear resistant friction materials. In this study, an appropriate sintered friction component for the synchronizer ring of a diesel manual transmission was developed, and its bonding characteristics were analyzed. That is, a process for bonding an Fe-based base material and Cu-based sintered friction material was developed. BSE and EDX analyses of this bonding layer were conducted, along with a shear strength test, to determine the bonding characteristics.