• ETRI Journal
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• v.35 no.4
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• pp.706-709
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• 2013

As an alternative to the traditional pilot-aided orthogonal frequency division multiplexing (OFDM), the time-domain pseudonoise (PN)-padded OFDM provides a higher spectral efficiency. However, the carrier frequency offset (CFO) attenuates peaks of the conventional PN correlation output, which limits the CFO estimation range of the OFDM synchronizer. An improved correlation is proposed in this letter to remove the CFO-induced amplitude attenuation of correlation peaks. For a synchronizer adopting the designed correlator, a larger range of CFO acquisition is obtained through using wider correlation windows with a smaller interval between them. The proposed method of CFO acquisition is verified in a digital terrestrial multimedia broadcast receiver, in which the synchronizer is able to acquire CFOs up to ${\pm}320$ kHz in the DVB-T F1 channel. Furthermore, the acquisition range can be expanded in more favorable channels.

• Journal of Communications and Networks
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• v.14 no.5
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• pp.501-509
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• 2012

This paper proposes a joint timing synchronization, channel estimation, and data detection for the impulse radio ultra-wideband systems. The proposed timing synchronizer consists of coarse and fine timing estimation. The synchronizer discovers synchronization points in two stages and performs adaptive threshold based on the maximum pulse averaging and maximum (MAX-PA) method for more precise synchronization. Then, iterative channel estimation is performed based on the discovered synchronization points, and data are detected using the selective rake (S-RAKE) detector employing maximal ratio combining. The proposed synchronizer produces two signals-the start signal for channel estimation and the start signal for start frame delimiter (SFD) detection that detects the packet synchronization signal. With the proposed synchronization, channel estimation, and SFD detection, an S-RAKE receiver with binary pulse position modulation binary phase-shift keying modulation was constructed. In addition, an IEEE 802.15.4a channel model was used for performance comparison. The comparison results show that the constructed receiver yields high performance close to perfect synchronization.

• IT SoC Magazine
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• s.8
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• pp.42-48
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• 2005

• Proceedings of the Microbiological Society of Korea Conference
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• 2002.10a
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• pp.206-208
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• 2002

• 제어로봇시스템학회:학술대회논문집
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• 1991.10b
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• pp.1817-1822
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• 1991

A method of reducing overhead caused by the processor synchronization process and common memory accesses in finely grained tasks is described. We propose a scheduler which considers the preparation time during searching to minimize the redundant accesses to shared memory. Since the suggested hardware (synchronizer) determines the access order of processors and bus arbitration simultaneously by including the synchronization process into the bus arbitration process, the synchronization time vanishes. Therefore this synchronizer has no overhead caused by the processor synchronization[l]. The proposed scheduler algorithm is processed in parallel. The processes share the upper bound derived by each searching and the lower bound function is built considering the preparation time in order to eliminate as many searches as possible. An application of the proposed method to a multi-DSP system to calculate inverse dynamics for robot arms, showed that the sampling time can be twice shorter than that of the conventional one.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.11
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• pp.2401-2408
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• 1997

The measured pulse shapes provided in the given data package demonstrated pulse distortions due to laser speckle. the distorted pulse shapes were carefully analyzed, modeled, and then applied to the DTTL(Digital-data Transition Tracking Loop)[1] bit synchronizer simulator to measure the mean time delay and its delay variation performance. The result showed that the maximum mean time delay variation with the modeled data was 12.5% when window size equals 1. All the data given were located within this modeled boundary and the maximum eman time delay variation was 7% in this case. The mean time delay variation was known to be smaller by reducing the window size [2][5][6]. The mitigated delay variation was 2.5% in the modeled case and 1.4% in the data set given when the windown size equals 0.1. With the digital DTTL insteal of analog DTTL, similar results was obtained.

• Proceedings of the KSRS Conference
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• 2008.10a
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• pp.228-231
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• 2008

For a satellite data communication, the technology of frame synchronization is widely used between a sender and a receiver. Last year, we suggested zero-loss frame synchronization [1] using pattern search and using bits threshold search algorithm that is based on SIMD technology [2,3]. This algorithm could solve both of hardware and software drawbacks, which are frame loss and low processing performance. However, this algorithm didn't optimize the processing of output data, synchronized data, which caused overhead to the memory allocation and the memory copy. Consequently, the performance of the frame synchronizer application was degraded. In this paper, we enhance previous work using a circular buffer in order to optimize the output data processing. The performance comparison with the previous algorithm shows that the enhanced proposed approach dramatically outperforms in the output data processing speed.

• Proceedings of the Korean Powder Metallurgy Institute Conference
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• 2006.09a
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• pp.132-133
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• 2006

Optimized choice of material for two principally different types of PM components is presented. The first is characterized by high stresses in areas with high stress concentrations (for example synchronizer hubs with very sharp notches, typically <0.25mm in the pre-synchronizer slot and the inner splines). The second type has slightly larger notch radii (small spur gears and sprockets with typically notch radii between 1- 3mm). Diffusion alloyed materials are well suited for sharp notch components. Pre-alloyed materials are also well suited for applications with sharp notches if compressive residual stresses in the notch roots are created by appropriate process control. A free choice of material is available for components with the larger notch radii.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.8
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• pp.883-890
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• 2015

As the semiconductor processing technology has been developing, multiple cores or NoC(network on chip) can be contained in recent chips. GALS(globally asychronous locally synchronous) clocking scheme that has multi-clock domains with different frequencies or phase differences is widely used to solve power consumption and clock skew in a large chip with a single clock. A synchronizer is needed to avoid a synchronization problem between sender and receiver in GALS. In this paper, the setup and hold time of DFF required to design the synchronizer are measured using 180nm CMOS processing parameters depending on temperature, supply voltage, and the size of inverter in DFF. The simulation results based on the bisection method in HSPICE show that the setup and hold time are proportional to temperature, however they are inversely proportional to supply voltage, and negative values are measured for the hold time.

• Journal of Advanced Navigation Technology
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• v.20 no.5
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• pp.453-461
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• 2016

Recently, with the growth of various sensor applications, the need of wireless communication systems which can support variable data rate is increasing. Therefore, advanced ZigBee (AZB) systems that support the various data rate under 250 kbps are proposed. However, the preamble structure for AZB systems causes the complexity increase of time synchronization circuits. In this paper, we propose preamble structure and time synchronization algorithm which can solve the problem of the complexity increase of time synchronization circuits. Implementation results show that the proposed time synchronizer for AZB systems include the logic slices of 6.92 k and, which are reduced at the rate of 62.3% compared with existing architecture.