• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.60-67
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• 2008

A low-power 2.4GHz fractional-N frequency synthesizer has been designed for 2.4GHz ISM band applications such as Bluetooth, Zigbee, and WLAN. To achieve low-power characteristic, the design has been focused on the power optimization of power-hungry blocks such as VCO, prescaler, and ${\Sigma}-{\Delta}$ modulator. An NP-core type VCO is adopted to optimize both phase noise and power consumption. Dynamic D-F/Fs with no static DC current are employed in designing the low-power prescaler circuit. The ${\Sigma}-{\Delta}$ modulator is designed using a modulus mapping circuit for reducing hardware complexity and power consumption. The designed frequency synthesizer which was fabricated using a $0.18{\mu}m$ CMOS process consumes 7.9mA from a single 1.8V supply voltage. The experimental results show that a phase noise of -118dBc/Hz at 1MHz offset, the reference spur of -70dBc at 25MHz offset, and the channel switching time of $15{\mu}s$ over 25MHz transition have been achieved. The designed chip occupies an area of $1.16mm^2$ including pads where the core area is only $0.64mm^2$.

• Journal of IKEEE
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• v.11 no.4
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• pp.129-136
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• 2007

In this paper, a simple but effective Dataline Redundancy Circuit (DRC) is proposed for a dual-port 1T-SRAM embedded in Display ICs. The DRC designed in the dual-port $320{\times}120{\times}18$-bit 1T-SRAM is verified in a 0.18-um CMOS 1T-SRAM process. In the DRC, because its control logic circuit can be implemented by a simple Shift Logic Circuit (SLC) with only an inverter and a NAND that is much simpler than the conventional, it can be placed in a pitch as narrow as a bit line pair. Moreover, an improved version of the SLC is also proposed to reduce its worst-case delay from 12.3ns to 5.9ns by 52%. By doing so, the timing overhead of the DRC can be hidden under the row cycle time because switching of the datalines can be done between the times of the word line setup and the sense amplifier setup. The area overhead of the DRC is estimated about 7.6% in this paper.

• Journal of IKEEE
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• v.11 no.4
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• pp.158-164
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• 2007

In this study, three types of a novel Trench IGBTs(Insulated Gate Bipolar Transistor) are proposed. The first structure has P-collector which is isolated by $SiO_2$ layer to enhance anode-injection-efficiency and enable the device to have a low on-state voltage drop(Von). And the second structure has convex P-base region between both gates. This structure may be effective to distributes electric-field crowded to gate edge. So this structure can have higher breakdown voltage(BV) than conventional trench-type IGBT(TIGBT). The process and device simulation results show improved on-state, breakdown and switching characteristics in each structure. The first one was presented lower on state voltage drop(2.1V) than that of conventional one(2.4V). Also, second structurehas higher breakdown voltage(1220V) and faster turn off time(9ns) than that of conventional structure. Finally, the last one of the proposed structure has combined the two structure (the first one and second one). This structure has superior electric characteristics than conventional structure about forward voltage drop and blocking capability, turnoff characteristics.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.40-49
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• 2008

A Frequency synthesizer for mobile-DTV applications is implemented using $0.18{\mu}m$ CMOS process with 1.8V supply. PMOS transistors are chosen for VCO core to reduce phase noise. The measurement result of VCO frequency range is 800MHz-1.67GHz using switchable inductors, capacitors and varactors. We use varactor bias technique for the improvement of VCO gain linearity, and the number of varactor biasing are minimized as two. VCO gain deterioration is also improved by using the varactor switching technique. The VCO gain and interval of VCO gain are maintained as low and improved using the VCO frequency calibration block. The sigma-delta modulator for fractional divider is designed by the co-simualtion method for accuracy and efficiency improvement. The VCO, PFD, CP and LF are verified by Cadence Spectre, and the sigma-delta modulator is simulated using Matlab Simulink, ModelSim and HSPICE. The power consumption of the frequency synthesizer is 18mW, and the VCO has 52.1% tuning range according to the VCO maximum output frequency. The VCO phase noise is lower than -100dBc/Hz at 1MHz at 1MHz offset for 1GHz, 1.5GHz, and 2GHz output frequencies.

• The Journal of the Korea Contents Association
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• v.20 no.2
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• pp.141-149
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• 2020

In this paper, I studied the relation between narrative construction (especially focusing on motif) and humor mechanism based on binge watching environment. Several motif theories such as B. Tomachevski, Horst and Ingrid Dämmrich and S. Chatman are used as a basic study method in chapter II. In popular sitcom , sometimes kernels(according to S. Chatman's term) in certain season's story are changed into satellites(according to S. Chatman's term) in other season's stories. The motif of Ross and Rachel's conflict is a representative example for this switching process. Especially on binge watching environment, as the interval length is much more shortened, viewers tend to reflect their own emotional memory into characters less strongly than segment watching environment. As a result, the possibility 'heavy' stories such as seperation are quickly changed into 'light' humorous matters is increased. This kind of hierarchy variation of repeated motif make the viewers laugh, because they can feel sudden liberating energy by eliminating psychological pressure. It means the characteristics of sitcom's humor on binge watching environment can also be explained by the theory of 'laugh as a eliminating tension', which I. Kant representatively said.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.1
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• pp.146-170
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• 2017

Joint channel assignment and routing is a well-known problem in multi-radio wireless mesh networks for which optimal configurations is required to optimize the overall throughput and fairness. However, other objectives need to be considered in order to provide a high quality service to network users when it deployed with high traffic dynamic. In this paper, we propose a re-configuration optimization model that optimizes the network throughput in addition to reducing the disruption to the mesh clients' traffic due to the re-configuration process. In this multi-objective optimization model, four objective functions are proposed to be minimized namely maximum link-channel utilization, network average contention, channel re-assignment cost, and re-routing cost. The latter two objectives focus on reducing the re-configuration overhead. This is to reduce the amount of disrupted traffic due to the channel switching and path re-routing resulted from applying the new configuration. In order to adapt to traffic dynamics in the network which might be caused by many factors i.e. users' mobility, a centralized heuristic re-configuration algorithm called State-Aware Joint Routing and Channel Assignment (SA-JRCA) is proposed in this research based on our re-configuration model. The proposed algorithm re-assigns channels to radios and re-configures flows' routes with aim of achieving a tradeoff between maximizing the network throughput and minimizing the re-configuration overhead. The ns-2 simulator is used as simulation tool and various metrics are evaluated. These metrics include channel-link utilization, channel re-assignment cost, re-routing cost, throughput, and delay. Simulation results show the good performance of SA-JRCA in term of packet delivery ratio, aggregated throughput and re-configuration overhead. It also shows higher stability to the traffic variation in comparison with other compared algorithms which suffer from performance degradation when high traffic dynamics is applied.

• Journal of Internet Computing and Services
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• v.18 no.5
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• pp.17-22
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• 2017

In a MPC coding using excitation source of voiced and unvoiced, it would be a distortion of speech waveform. This is caused by normalization of synthesis speech waveform of voiced in the process of restoration the multi-pulses of representation section. This paper present PCFBD-MPC( Position Compensation Frequency Band Division-Multi Pulse Coding ) used V/UV/S( Voiced / Unvoiced / Silence ) switching, position compensation in a multi-pulses each pitch interval and Unvoiced approximate-synthesis by using specific frequency in order to reduce distortion of synthesis waveform. Also, I was implemented that the PCFBD-MPC( Position Compensation Frequency Band Division-Multi Pulse Coding ) system and evaluate the SNRseg of PCFBD-MPC in coding condition of 8kbps. As a result, SNRseg of PCFBD-MPC was 13.4dB for female voice and 13.8dB for male voice respectively. In the future, I will study the evaluation of the sound quality of 8kbps speech coding method that simultaneously compensation the amplitude and position of multi-pulse source. These methods are expected to be applied to a method of speech coding using sound source in a low bit rate such as a cellular phone or a smart phone.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.4A
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• pp.356-368
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• 2011

While most of the public radio spectrum bands are allocated to licensed users, cognitive radio has been considered as a promising technology for the efficient spectrum utilization. In this new technology, secondary users opportunistically use the temporally underutilized licensed bands as long as they do not give the harmful interference to primary users. In this paper, we focus on the infra-structured network condition in which the cognitive radio network consists of a cognitive radio base station and multiple secondary users. Upon detecting a primary user, the entire cognitive radio network generally switches to another available channel, even if most of the on-going communications still does not interfere with the primary user. Moreover, the network re-entry process on a new channel causes the service disruption of the on-going communications. For this reason, in this paper, we propose a relaying scheme for efficient frequency usage, in which the secondary user out of the interference range of a primary user performs as a relaying node for the secondary user possibly interfering with a primary user. The entire spectrum switching is not required, and thus, we can avoid the service disruption of the on-going communications as much as possible.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.6
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• pp.613-624
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• 2011

An MMIC multi-function chip for an X-band active phased array radar system has been designed and fabricated using a 0.5 ${\mu}m$ GaAs p-HEMT commercial process. A digital serial-to-parallel converter is included in this chip in order to reduce the number of the control interface. The multi-function chip provides several functions: 6-bit phase shifting, 6-bit attenuation, transmit/receive switching, and signal amplification. The fabricated multi-function chip with a relative compact size of 24 $mm^2$(6 mm${\times}$4 mm) exhibits a transmit/receive gain of 24/15 dB and a P1dB of 21 dBm from 8.5 GHz to 10.5 GHz. The RMS errors for the 64 states of the 6-bit phase shift and attenuation were measured to $7^{\circ}$ and 0.3 dB, respectively over the frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10A
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• pp.1113-1122
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• 2004

This paper is basically to achieve the high-availability and high-reliability of the control system from the implementation of the fault-tolerant system using the hot-standby sparing technique. To meet the objective, we design and implement a board with fault tolerance I/O bus to detect the fault. Warm-standby sparing technique is the fault tolerance technique usually used for switching control system in present. This technique can be easily implemented, but can not detect the fault quickly and can malfunction because of the hardware fault. The hot-standby sparing fault tolerant technique implemented in this paper is consists of dual processor modules and a I/O processor using fault tolerant I/O bus. The proposed method can find the faults as soon as possible, so it can prevent from wrong operation. Also it is possible to normal re-service due to the short recovering time. To implement the fault-tolerant dual system with fault detection be, two daughter, called FTMA and FTIA, boards designed and implemented are applied to the system. And we also simulated the proposed method to verify the high-availability and high-reliability of the control system using Markov process.