• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.1
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• pp.1-7
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• 2007

Generally, an electric railroad feeding system has many problems due to the different characteristics in contrast with a load of general three-phase AC electric power system. One of them is harmonics problem caused by the switching device existing in the feeding system, and moreover, the time-varying dynamic loads of rail way is inherently another cause to increase this harmonics problem. In Korea power systems, the electric railroad feeding system is directly supplied from the substation of KEPCO. Therefore, if voltages fluctuation or unbalanced voltages are created by the voltage and current distortion or voltage drop during operation, it affects directly the source of supply. The trainloads of electric railway system have non-periodic but iterative harmonic characteristics as operating condition, because the electric characteristic of the electric railroad feeding system is changed by physical conditions of the each trainload. According to the traditional study, the estimation of harmonics has been performed by deterministic way using the steady state data at the specific time. This method is easy to analyze harmonics, but it has limits in some cases which needs an assessment of dynamic load and reliability. Therefore, this paper proposes the probabilistic estimation method, moments matching method(MW) in order to overcome the drawback of deterministic method. In this paper, distributions for each harmonics are convolved to obtain the moments and cumulants of TDD(Total Demand Distortion), and this can be generalized for any number of trains. For the case study, the electric railway system of LAT(Intra Airport Transit) in Incheon International Airport is modeled using PSCAD/EMTDC dynamic simulator. The raw data of harmonics for the moments matching method is acquired from simulation of the LAT model.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.5
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• pp.455-461
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• 2017

In this paper, a local DL (Data Line) sensing method with smaller parasitic capacitance replacing the previous distributed DB sensing method with large parasitic capacitance is proposed to reduce the time to transfer BL (Bit Line) voltage to DL in the read mode. A new BL switching circuit turning on NMOS switches faster is also proposed. Furthermore, the access time is reduced to 35.63ns from 40ns in the read mode and thus meets the requirement since BL node voltage is clamped at 0.6V by a DL clamping circuit instead of precharging the node to VDD-VT and a differential amplifier are used. The layout size of the designed 512Kb EEPROM memory IP based on a $0.13{\mu}m$ BCD is $923.4{\mu}m{\times}1150.96{\mu}m$ ($=1.063mm^2$).

• Journal of Advanced Navigation Technology
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• v.13 no.1
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• pp.54-61
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• 2009

In this paper, Switching to digital TV broadcasting and mobile operators license expiration period of the frequency, time and 700MHz, 800MHz and 900MHz frequency band plan for the redistribution is actively being discussed. Redistribution policy direction of these frequency 800MHz (bandwidth 10MHz) integrated command frequency for wireless networks(i.e TETRA) is expected to be considered a redistribution. These Integrated Wireless Network Infrastructure configurations at the time and data communication capabilities of the system unwilling TETRA Release 2 standard for the system is presented. This system is analyzed that Release 1 of the existing system takes up more than 6 times the increase of frequency bands. Therefore, integration of the frequency band assigned to the command of a wireless network with the introduction of advanced systems will not be able to do. In this paper to the digital TV transition, and the policy based on analysis of trends in the 700MHz band for the integration of wireless networks, provides policy direction for the allocation plan.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.12-21
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• 2004

Error control is one of major concerns in many electronic systems. Experience shows that most malfunctions during system operation are caused by transient faults, which often mean abnormal signal delays that may result in violations of circuit element timing constraints. This paper presents a novel CMOS-based concurrent timing error detector that makes a flip-flop to sense and then signal whether its data has been potentially corrupted or not by a setup or hold timing violation. Designed circuit performs a quiescent supply current evaluation to determine timing violation from the input changes in relation to a clock edge. If the input is too close to the clock time, the resulting switching transient current in the detection circuit exceeds a reference threshold at the instant of the clock transition and an error is flagged. The circuit is designed with a $0.25{\mu}m$ standard CMOS technology at a 2.5 V supply voltage. The validity and effectiveness are verified through the HSPICE simulation. The simulation results in this paper shows that designed circuit can be used to detect setup and hold time violations effectively in clocked circuit element.

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.6
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• pp.625-630
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• 2010

With regard to the examples of establishing various sorts of information security, it can be seen that there are gradual, developmental procedures including Firewall and VPN (Virtual Private Network), IDS (Intrusion Detection System), or ESM(Enterprise Security Management). Each of the security solutions and equipments analyzes both defense and attack for information security with the criteria of classifying the problems of security policies by TCP/IP layers or resulted from attack patterns, attack types, or invasion through specialized security technology. The direction of this study is to examine latency time vulnerable to invasion which occurs when L2-stratum or lower grade equipments or policies are applied to the existing network through TCP/IP layer's L3-stratum or higher grade security policies or equipments and analyze security holes which may generate due to the IP preoccupation in the process of establishing policies to limit particular IP area regarding the policies for security equipments to figure out technological problems lying in it.

• Journal of Periodontal and Implant Science
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• v.41 no.5
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• pp.211-217
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• 2011

Purpose: The marginal bone levels around implants following restoration are used as a reference for evaluating implant success and survival. Two design concepts that can reduce crestal bone resorption are the microthread and platform-switching concepts. The aims of this study were to analyze the placement of microthreaded and platform-switched implants and their short-term survival rate, as well as the level of bone around the implants. Methods: The subjects of this study were 27 patients (79 implants) undergoing treatment with microthreaded and platform-switched implants between October 2008 and July 2009 in the Dental Hospital of Yonsei University Department of Periodon-tology. The patients received follow-up care more than 6 months after the final setting of the prosthesis, at which time periapical radiographs were taken. The marginal bone level was measured from the reference point to the lowest observed point of contact between the marginal bone and the fixture. Comparisons were made between radiographs taken at the time of fixture installation and those taken at the follow-up visit. Results: During the study period (average of 11.8 months after fixture installation and 7.4 months after the prosthesis delivery), the short-term survival rate of microthreaded and platform-switched implants was 100% and the marginal bone loss around implants was $0.16{\pm}0.08$ mm, the latter of which is lower than the previously reported values. Conclusions: This short-term clinical study has demonstrated the successful survival rates of a microthread and platform-switched implant system, and that this system is associated with reduced marginal bone loss.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.2
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• pp.307-312
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• 2000

Asynchronous transfer mode(ATM) is flexible to support the various multimedia communication services such as data, voice, and image by applying asynchronous time-sharing and statistical multiplexing techniques to the existing data communication. ATM service is categorized to CBR, VBR, UBR, and ABR according to characteristics of the traffic and a required service qualities. Among them, ABR service guarantees a minimal bandwidth and can transmit cells at a maximum transmission rate within the available bandwidth. To minimize the cell losses in transmission and switching, a feedback information in ATM network is used to control the traffic. In this paper, predictive control algorithms are proposed for the feedback information. When the feedback information takes a long propagation delay to the backward nodes, ATM switch can experience a congestion situation from the queue length increases, and a high queue length fluctuations in time. The control algorithms proposed in this paper provides predictive control model using slop changes of the queue length function and previous data of the queue lengths. Simulation shows the effectiveness result of the proposed control algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.31-36
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• 2004

In this paper, we proposed the new structure of the Rake Finger using Walsh Switch, the shared accumulator, and the pipeline-FWHT algorithm for reducing the signal processing complexity resulting from the increase of the number of data correlator. The function simulation of the proposed architecture is performed by Synopsys tool and the timing simulation is performed by Compass tool. The number of computational operation in the proposed data correlators is 160 additions and the conventional ones is 512 additions when the number of walsh code N=4. As a result, it is reduced about 3.2 times other than the number of computational operation of the conventional ones. Also, the result shows that the data processing time of the proposed Rake Finger architecture is 90,496[ns] and the conventional ones is 110,696[ns]. It is $18.3\%$ faster than the data processing time of the conventional Rake Finger architecture.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.4 s.310
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• pp.23-30
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• 2006

This paper presents design andd verification of a circuit that improves the control-operation problems of Stored Program Optical Computer (SPOC), which is an optical computer using $LiNbO_3$ optical switching element. Since the memory of SPOC takes the Delay Line Memory (DLM) architecture and instructions that are needless of operands should go though memory access stages, SPOC memory have problems; it takes immoderate access time and unnecessary operations are executed in Arithmetic Logical Unit (ALU) because desired operations can't be selectively executed. In this paper, improvement on circuit has been achieved by removing the memory access of instructions that are needless of operands by decoding instructions before locating operand. Unnecessary operations have been reduced by sending operands to some specific operational units, not to all the operational units in ALD. We show that total execution time of a program is minimized by using the Dual Instruction Register(DIR) architecture.

• Journal of Industrial Technology
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• v.40 no.1
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• pp.13-18
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• 2020

Lithium-ion batteries have a small volume, light weight and high energy density, maximizing the utilization of mobile devices. It is widely used for various purposes such as electric bicycles and scooters (e-Mobility), mass energy storage (ESS), and electric and hybrid vehicles. To date, lithium-ion batteries have grown to focus on increasing energy density and reducing production costs in line with the required capacity. However, the research and development level of lithium-ion batteries seems to have reached the limit in terms of energy density. In addition, the charging time is an important factor for using lithium-ion batteries. Therefore, it was urgent to develop a high-speed charger to shorten the charging time. In this thesis, a discharger was fabricated to evaluate the capacity and characteristics of Li-ion battery pack which can be used for e-mobility. To achieve this, a smart discharger is designed with a combination of active load, current sensor, and temperature sensor. To carry out this thesis, an active load switching using sensor control circuit, signal processing circuit, and FET was designed and manufactured as hardware with the characteristics of active discharger. And as software for controlling the hardware of the active discharger, a Raspberry Pi control device and a touch screen program were designed. The developed discharger is designed to change the 600W capacity battery in the form of active load.