• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.398-399
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• 2019

This paper presents a method of the circuit design of the multiple-valued digital logic switching functions based on the modular techniques. Fisr of all, we introduce the necessity, background and concepts of the modular design techniques for the digital logic systems. Next, we discuss the definitions that are used in this paper. For the purpose of the circuit design for the multiple-valued digital logic switching functions, we discuss the extraction of the partition functions. Also we describe the construction method of the building block, that is called the modules, based on each partition functions. And we apply the proposed method to the example, we compare the results with the results of the earlier methods. In result, we decrease the control functions, it means that we obtain the effective cost in the digital logic design for any other earlier methods. In the future research, we require the universal module that traet more partition functions and more compact module.

• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.67-75
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• 1997

This paper presents a virtual-parallel multistage interconnection network (MIN) which provides multipath between processor and memory module. The proposed virtual-parallel MIN network which uses $m{\times}1$ mutiplexer at the input switching block, $1{\times}m$ demultiplexer at the output switching block and logN-1 switching stages has maximum $2{\times}m$ unique paths between processor and memory module. Because it has multi-redundance paths, a number of processors can connect a specific Also, this new virtual-parallel structured MIN network can reduce packet collision possibility at switching block and it has cost. It shown to improve a performance and to be a very simple structure in comparision with MBSF structured MIN.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.543-547
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• 2000

Power factor and harmonics are increasingly important for high speed train auxiliary block. This paper presents experimental results of the power factor and harmonic performance of two parallel PWM circuits under various supply and load conditions. For reducing harmonics the harmonic content is eliminated by the phase shift between two converters switching phase. Experimental results show the usefulness of the proposed method and applicability to PWM converter in auxiliary block of high speed train.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.274-277
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• 2000

Power factor and harmonics are increasingly important for high speed train auxiliary block. This paper presents experimental results of the power factor and harmonic performance of four parallel PWM converter circuits under various supply and load conditions. For reducing harmonics the harmonic content is eliminated by the phase shift between four converters switching phase. Experimental results show the usefulness of the proposed method and applicability to PWM converter in auxiliary block of high speed train.

• Journal of Korea Society of Industrial Information Systems
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• v.27 no.5
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• pp.25-36
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• 2022

This paper proposes a random sign reversal technique in space frequency block code for single carrier modulation. The traditional space time and frequency block coding technique may be confronted with radio environments openly, severe radio hijacking problems are to be overcome. In order to avoid such an open radio issue, random coded data protection technique for space-time block code was proposed, but this algorithm can change channel combination per an Orthogonal Frequency Division Multiplexing block. This kind of slow switching increases the probability that nearby receivers will detect the transmitted data. This paper proposes a fast switching algorithm per data symbols' basis which is a random sign reversal technique in space frequency block code for Single Carrier Modulation. It is shown in simulation that the proposed one has a superior performance in comparison with the performance of the receiver which do not know the random timing sequence of sign reversal.

• Journal of Communications and Networks
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• v.15 no.3
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• pp.292-300
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• 2013

Nowadays, energy saving has become a hot topic and information and communication technology has become a major power consumer. In long term evolution advanced (LTE-A) networks, heterogeneous deployments of low-power nodes and conventional macrocells provide some new features, such as coverage extension, throughput enhancement, and load balancing. However, a large-scale deployment of low-power nodes brings substantial energy consumption and interference problems. In this paper, we propose a novel switching strategy (NS), which adaptively switches on or off some low-power nodes based on the instantaneous load of the system. It is compatible with the microcells' load balancing feature and can be easily implemented on the basis of existing LTE-A specifications. Moreover, we develop an analytical model for analyzing the performance of system energy consumption, block rate, throughput, and energy efficiency. The performance of NS is evaluated by comparison with existing strategies. Theoretical analysis and simulation results show that NS not only has a low block rate, but also achieves a high energy efficiency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.1-10
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• 2008

In this paper, we describe a design of a 128bit MRAM based on a new switching architecture which is Local Field Switching(LFS). LFS uses a local magnetic field generated by the current flowing through an MTJ. This mode reduces the writing current since small current can induce large magnetic field because of close distance between MTJ and the current. It also improves the cell selectivity over using conventional MTJ architecture because it doesn't need a digit line for writing. The MRAM has 1-Transistor 1-Magnetic Tunnel Junction (IT-1MTJ) memory cell structure and uses a bidirectional write driver, a mid-point reference cell block and a current mode sense amplifier. CMOS emulation cell is adopted as an LFS-MTJ cell to verify the operation of the circuit without the MTJ process. The memory circuit is fabricated using a $0.18{\mu}m$ CMOS technology with six layers o) metal and tested on custom board.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.6
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• pp.385-393
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• 2017

As the use of mobile devices such as smartphones increases, there is growing interest on the benefits of virtualization in embedded systems. Full virtualization has the advantage of running the guest virtual machine without modifying the guest operating system. However, full virtualization suffers slow execution speed due to the cost of context switching between the virtual machines and the virtual machine monitor. In this paper, we propose a translated block and context switching optimization to improve the guest execution speed in the embedded system. As a result, the improved dynamic binary translator is up to 5.95 times faster than the native execution. Performance degradation is less than that of the other virtualization system.

• ETRI Journal
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• v.18 no.4
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• pp.229-244
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• 1997

Realization of the economical, reliable, and efficient ATM interface block becomes an important key to development of the ATM switching system when we consider new issues raised recently. In this paper, we summarize requirements for the ATM interface block and present the UNI (User Network Interface)/NNI (Network Node Interface) architecture to meet these requirements. We also evaluate the performance of the multiplexer adopting the various multiplexing schemes and service disciplines. For ATM UNI/NNI interface technologies, we have developed a new policing device using the priority encoding scheme. It can reduce the decision time for policing significantly. We have also designed a new spacer that can space out the clumped cell stream almost perfectly. This algorithm guarantees more than 99 % conformance to the negotiated peak cell rate. Finally, we propose the interface architecture for accommodation of the ABR (Available Bit Rate) transfer capability. The proposed structure that performs virtual source and virtual destination functions as well as a switch algorithm can efficiently accommodate the ABR service.

• Journal of the Korean Operations Research and Management Science Society
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• v.22 no.2
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• pp.139-151
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• 1997

An ATM switching system may be designed so that communications between processors of its control part can be performed via its switching network rather than a separate inter-processor communications (IPC) network. In such a system, there should be interfaces to convent IPC traffic from message format to cell format and vice versa, that is, mechanisms to perform the SAR (Segmentation And Reassembly) sublayer functions. In this paper, we concern the cell reassembly mechanism among them, mainly focussed on buffer management schemes. We consider a few alternatives to implement cell reassembly function block, namely, separated buffering, reserved buffering and shared buffering in this paper. In case of separated and reserved buffering, we employ a continuous time Markov chain for the performance evaluation of cell reassembly mechanism, judicially defining the states of the mechanism. Performance measures such as measage loss probability, mean number of message queued in buffer and average reassembly delay are obtianed in closed forms. In case of shared buffering, we compare the alternatives for implementing cell reassembly function block using simulation because it is almost impossible to analyze the mechanism of shared buffering by analytical modeling. Some illustrations are given for the performance analysis of the alternatives to implement cell reassembly function block.