• Journal of Power Electronics
• /
• 제15권3호
• /
• pp.587-601
• /
• 2015

A high step-up dc-dc converter is proposed for photovoltaic power systems in this paper. The proposed converter consists of an input current doubler, a symmetrical switched-capacitor doubler and an active-clamp circuit. The input current doubler minimizes the input current ripple. The symmetrical switched-capacitor doubler is composed of two symmetrical quasi-resonant switched-capacitor circuits, which share the leakage inductance of the transformer as a resonant inductor. The rectifier diodes (switched-capacitor circuit) are turned off at the zero current switching (ZCS) condition, so that the reverse-recovery problem of the diodes is removed. In addition, the symmetrical structure results in an output voltage ripple reduction because the voltage ripples of the charge/pump capacitors cancel each other out. Meanwhile, the voltage stress of the rectifier diodes is clamped at half of the output voltage. In addition, the active-clamp circuit clamps the voltage surges of the switches and recycles the energy of the transformer leakage inductance. Furthermore, pulse-width modulation plus phase angle shift (PPAS) is employed to control the output voltage. The operation principle of the converter is analyzed and experimental results obtained from a 400W prototype are presented to validate the performance of the proposed converter.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1995년도 하계학술대회 논문집 A
• /
• pp.315-317
• /
• 1995

A simple drive circuit without position sensors for a switched reluctance motor is presented. The turn on and turn off points are determined by detecting the rate of change of the active phase current. The drive circuit consists of a current sensing resistor, RC filter, comparator, OP Amp, and OR gates. It is verified through the experiments that the switched reluctance motor with the proposed sensorless drive circuit is well operated in wide speed ranges.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 1999년도 전력전자학술대회 논문집
• /
• pp.626-630
• /
• 1999

A new integrated single-stage zero current switched(ZCS) quasi-resonant converter (QRC) for the power factor correction(PFC) converter is introduced in this paper. The power factor correction can be achieved by the discontinuous conduction mode(DCM) operation of an input current. The proposed converter has the characteristics of the good power factor, low line current harmonics, and tight output regulation. Furthermore, the ringing effect due to the output capacitance of the main switch can be eliminated by use of active clamp circuit.

• 전기학회논문지
• /
• 제59권10호
• /
• pp.1839-1844
• /
• 2010

A power management controller circuit with switched capacitor mode down regulator and battery charger block for semi-active RFID tags was proposed and fabricated. The main purposes of the proposed switched capacitor mode down regulator and battery charger block are to reduce standby current and to provide a self-controlled thin film battery charger by detecting the received RF power, respectively. Fabricated chip area is $360,000{\mu}m^2$ and measured standby current was about $1.3{\mu}A$. To further reduction of standby current, a wake-up circuit has to be included in the power management controller.

• 한국지능시스템학회:학술대회논문집
• /
• 한국퍼지및지능시스템학회 2007년도 춘계학술대회 학술발표 논문집 제17권 제1호
• /
• pp.485-488
• /
• 2007

최근 Analog Sampled-Data 신호처리를 위하여 주목되고 있는 SI(Switched-Current) circuit은 저전력 동작을 하는 장점이 있지만, 반면에 SI circuit에서의 기본 회로인 Current Memory는 Charge Injection에 의한 Clock Feedthrough이라는 치명적인 단점을 갖고 있다. 따라서 본 논문에서는 Current Memory의 문제점인 Clock Feedthrough의 일반적인 해결방안으로 Dummy Switch의 연결을 검토하였고, Austria Mikro Systeme(AMS)에서 $0.35{\mu}m$ CMOS process BSIM3 Model로 제작하기 위하여 Current Memory의 Switch MOS와 Dummy Switch MOS의 적절한 Width을 정의하여야 하므로, 그 값을 도출하였다. Simulation 결과, Switch의 Width는 $2{\mu}m$, Dummy Switch의 Width는 $2.35{\mu}m$로 정의될 수 있음을 확인하였다.

• 대한전자공학회논문지SD
• /
• 제49권1호
• /
• pp.15-24
• /
• 2012

본 논문에서는 Switched-Capacitor 지연 기법의 새로운 고해상도 DPWM 발생기를 사용한 Dynamic-Response-Free SMPS를 제안한다. 제안된 회로는 Switched-Capacitor 지연 기법을 이용한 DPWM 발생기의 내부 커패시터 전압 기울기를 제어하는 방식으로 DPWM의 duty ratio를 결정한다. 제안된 회로는 컨버터의 피드백 전압과 기준전압을 비교하여 DPWM 발생기의 내부 캐패시터에 충방전되는 전류량을 제어하는 방식으로 출력전압 tracking이 가능하다. 따라서 제안된 회로는 기존 closed loop 제어 방식의 SMPS들에서 문제점이 되고 있는 동적 응답특성을 고려할 필요가 없으며, 출력 전압에 overshoot/undershoot로 인한 ringing 현상이 발생하지 않는다는 큰 장점을 가진다. 제안된 회로는 1MHz~10MHz까지 스위칭주파수를 사용자가 선택할 수 있으며, 100MHz의 내부 제어 동작 주파수로 10MHz 최대 스위칭 주파수(DPWM) 발생이 가능하다. 100MHz의 내부 제어 동작 주파수를 사용하여 10MHz 스위칭 주파수 발생시 소모되는 내부 회로의 최대 전류는 2.7mA이며, 출력 버퍼를 포함한 전체 시스템의 전류 소모는 15mA이다. 제안된 회로는 0.125%의 DPWM duty ratio 해상도를 가지고 부하에 최대 1A까지 전류공급이 가능하며, 최대 리플 전압은 8mV이다. 동부하이텍 BCD $0.35{\mu}m$ 공정 파라미터를 이용해 시뮬레이션을 수행하여 제안된 회로의 동작을 검증하였다.

• 한국지능시스템학회:학술대회논문집
• /
• 한국지능시스템학회 2008년도 춘계학술대회 학술발표회 논문집
• /
• pp.247-250
• /
• 2008

최근 무선통신용 LSI는 배터리 수명과 관련하여, 저전력 동작이 중요시되고 있다. 따라서 Digital CMOS 신호처리와 더불어 동작 가능한 SI (Switched-Current) circuit를 이용하는 Current-mode 신호처리가 주목받고 있다. 그러나 SI circuit의 기본인 Current Memory는 Charge Injection에 의한 Clock Feedthrough라는 문제점을 갖고 있기 때문에, 전류 전달에 있어서 오차를 발생시킨다. 본 논문에서는 Current Memory의 문제점인 Clock Feedthrough의 해결방안으로 CMOS Switch의 연결을 검토하였고, 0.25${\mu}m$ CMOS process에서 Memory MOS와 CMOS Switch의 Width의 관계는 simulation 결과를 통하여 확인하였으며, MOS transistor의 관계를 분명히 하여, 설게의 지침을 제공한다.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
• /
• 제54권9호
• /
• pp.431-436
• /
• 2005

This paper studies a novel boost DC-DC converter operated high efficiency for discontinuous current mode (DCM) control. The converter worked in DCM eliminates the complicated circuit control requirement, reduces a number of components, and reduces the used reactive components size. In the general DCM converter, the switching devices are turned-on the zero current switching (ZCS), and the switching devices must be switched-off at a maximum reactor current. To achieve the zero voltage switching (ZVS) at the switching turn-off, the proposed converter is constructed by using a new loss-less snubber circuit. Soft-switched operation of the proposed boost converter is verified by digital simulation and experimental results. A new boost converter achieves the soft-switching for all switching devices without increasing their voltage and current stresses. The result is that the switching loss is very low and the efficiency of boost DC-DC converter is high.

• Journal of Power Electronics
• /
• 제15권1호
• /
• pp.31-38
• /
• 2015

In this paper, a buck-boost type battery charger is developed for charging battery set with a lower voltage. This battery charger is configured by a rectifier circuit, an integrated boost/buck power converter and a switched capacitors circuit. A boost power converter and a buck power converter sharing a common power electronic switch are integrated to form the integrated boost/buck power converter. By controlling the common power electronic switch, the battery charger performs a hybrid constant-current/constant-voltage charging method and gets a high input power factor. Accordingly, both the power circuit and the control circuit of the developed battery charger are simplified. The switched capacitors circuit is applied to be the output of the boost converter and the input of the buck converter. The switched capacitors circuit can change its voltage according to the utility voltage so as to reduce the step-up voltage gain of the boost converter when the utility voltage is small. Hence, the power efficiency of a buck-boost type battery charger can be improved. Moreover, the step-down voltage gain of the buck power converter is reduced to increase the controllable range of the duty ratio for the common power electronic switch. A prototype is developed and tested to verify the performance of the proposed battery charger.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1995년도 하계학술대회 논문집 A
• /
• pp.325-327
• /
• 1995

A new gate drive circuit of classic converter for a switched reluctance motor is presented. Conventional gate drive circuit usually consists of the isolated power supplies and signal transferring devices for isolation, such as photo coupler, pulse transformer, and gate drive chips. The proposed gate drive circuit consists of resistors, capacitors, and zenor diodes without isolated power supplies, that make the drive circuit simple and reduce the material cost. The operational modes are classified and analyzed. The characteristics of the phase current and the gate signal of upper switches is investigated with the variation of duty ratio through the experiments.