• Journal of Electrical Engineering and Technology
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• v.12 no.4
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• pp.1471-1483
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• 2017

The low-frequency characteristics of four-switch three-phase (FSTP) inverter are investigated in this paper. Firstly, a general space vector pulse width modulation (SVPWM) directly involved the neutral point voltage of DC-link is proposed, where no sector identifications and trigonometric function calculations are needed. Subsequently, to suppress the DC offset in the neutral point voltage, the relationship between the neutral point voltage and the ${\beta}-axis$ component of the load current is derived, and then a new neutral point voltage control scheme is proposed where no low pass filter is adopted. Finally, the relationship between the load power factor and the maximum linear modulation index of the FSTP inverter is revealed. Since the operational region for the FSTP inverter in low frequency is reduced by the enlarged amplitude of the neutral point voltage, a linear modulation range enlargement scheme is proposed. A permanent magnet synchronous motor with preset rotary speed serves as the low-frequency load of the FSTP inverter. Experimental results verify that the new neutral point voltage control scheme is effective in the deviation suppression of the neutral point voltage, and the proposed scheme is able to provide a larger linear operational region in low frequency.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.58 no.3
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• pp.303-309
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• 2009

Switched Reluctance Motor(SRM) has become popular for industrial application, particularly for low medium drives due to the advantages of SRM over the other ac motors: SRM can be manufactured with low cost because it has a simple structure. But, asymmetric bridge converter that generally is used for driving requires two discrete switching devices and freewheeling diodes per phase, and cause the SRM drives to be complicated and to increase the cost of overall system. Therefore, this paper suggests a new type of 4-switch converter for SRM. 4-switch converter topology is studied to provide a possibility for the realization of low cost 3-phase SRM drive system. For effective utilization of the developed system, a new current control algorithm is designed and implemented to produce the desired dynamic performance. With the developed power conversion circuit and control scheme, it is expected that the proposed system can be widely used in commercial applications with reduced system cost.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.2
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• pp.268-275
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• 2015

This paper proposes a method of switching to improve power loss for the single-phase three-level NPC inverter. The conventional switching methods, which are called as the bipolar and unipolar switching methods, are used for single phase inverters using three-level topology. However, these switching method have disadvantage in the power loss. Because all of the switch are operated. To reduce the power loss of the three-level NPC inverter, clamp switching method is introduced in this paper. This way, one of the lag is fixed that switching loss is reduced. This paper analyzes and compares power losses of unipolar method and clamp method. The validity of the power loss analysis is verified through the simulation and experimental results.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.4
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• pp.1-11
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• 1981

This paper proposes a method of generalizing the clocking scheme in the Switched Capacitor Filter(SCF) design using Voltage Inverter Switches (VIS's). Parallel RC and RL elements, and parallel LC resonators can be implemented by the proposed clocking schemes Applying these new elements and the generalized clocking schemes to the SCF design, the total number of required operational amplifiers and capacitors can be reduced. Experimental results of a band- stop filter and a low-pass filter using a new type grounded VIS show good agreements with t he theoretical characteristics.

• Journal of Power Electronics
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• v.18 no.2
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• pp.522-532
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• 2018

The cascaded H Bridge (CHB) multilevel inverter (MLI) is popular among the classical MLI topologies due to its modularity and reliability. Although space vector modulation (SVM) is the most suitable modulation scheme for MLIs, it has not been used widely in industry due to the higher complexity involved in its implementation. In this paper, a simple and novel generalized SVM algorithm is proposed, which has both reduced time and space complexity. The proposed SVM involves the generalization of both the duty cycle calculation and switching sequence generation for any n-level inverter. In order to generate the gate pulses for an inverter, a generalized switch matrix (SM) for the CHB inverter is also introduced, which further simplifies the algorithm. The algorithm is tested and verified for three-phase, three-level and five-level CHB inverters in simulations and hardware implementation. A comparison of the proposed method with existing SVM schemes shows the superiority of the proposed scheme.

• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.2
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• pp.111-120
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• 2002

The multi-level inverter system is very promising in ac drives, when both reduced harmonic contents and high power are required. In case of multi-level inverter system, the loss of switch devices cannot be analyzed by conventional methods. The reason is that the loss of each the switch device is different from one another unlike 2-level. In this paper, a simple and accurate method of computing conduction and switching loss is proposed for multi-level inverter system. The validity of the proposed method is proven for 3-level and 4-revel diode clamped inverter system.

• Proceedings of the KIPE Conference
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• 2004.07a
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• pp.260-264
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• 2004

In this paper the novel converter topology for the switched reluctance motor drives is proposed, which is composed of the minimum switch per phase and is connected to the single-phase voltage inverter for ac voltage source. The proposed converter topology is divided into two types according to the voltage source inverter of half bridge type and full bridge type. Proposed converters of two types are proposed, analyzed and compared with each other. The SRM using proposed converter maintain the hi인 efficiency though the power switches are reduced.

• Journal of Electrical Engineering and Technology
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• v.11 no.6
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• pp.1674-1683
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• 2016

In this paper, a Finite Control Set Model Predictive Control (FCS-MPC) for a five level cascaded multilevel inverter (CMLI) with reduced switch topology is proposed. Five switches are used here instead of conventionally used eight switches. The main contribution of this paper is to make the MPC controller work for the reduced switch topology using only 19 voltage vectors in place of conventional 61 voltage vectors for a five level CMLI. This simplifies the execution of the MPC algorithm, paving a way for the significant reduction in the computational time. The controller makes use of the excellent ability of MPC to multitask, by adding one more objective which is to reduce the average switching frequency in addition to controlling the load current. This is especially important, since switching losses and therefore switching frequency is significant for high-power applications. The trade-off of this MPC is that the current is not as smooth as the 61 vector scheme, but well within the limits of IEEE standards. The results shown prove that this MPC works well in steady state and dynamic conditions too.

• Journal of Power Electronics
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• v.9 no.4
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• pp.593-603
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• 2009

This paper proposes and describes the design and operational principles of a three-phase three-level nine switch voltage source inverter. The proposed topology consists of three bi-directional switches inserted between the source and the full-bridge power switches of the classical three-phase inverter. As a result, a three-level output voltage waveform and a significant suppression of load harmonics contents are obtained at the inverter output. The harmonics content of the proposed multilevel inverter can be reduced by half compared with two-level inverters. A Fourier analysis of the output waveform is performed and the design is optimized to obtain the minimum total harmonic distortion. The full-bridge power switches of the classical three-phase inverter operate at the line frequency of 50Hz, while the auxiliary circuit switches operate at twice the line frequency. To validate the proposed topology, both simulation and analysis have been performed. In addition, a prototype has been designed, implemented and tested. Selected simulation and experimental results have been provided.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1552-1557
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• 2015

The paper unleashes a new idea to arrive at reduced switch count topological structures configured in the form of a matrix for a cascaded Multi level inverter (CMLI). The theory encircles to minimize the number of switches involved in the conduction path and there from acclaim reduced input current distortion, lower switching losses and electromagnetic interference. The focus extends to standardize the number of power devices required for reaching different levels of output voltage from the same architecture. It includes appropriate pulse width modulation (PWM) strategy to generate firing pulses and ensure the desired operation of the power modules. The investigative study carries with it MATLAB based simulation and experimental results obtained using suitable prototypes to illustrate the viability of the proposed concept. The promising nature of the performance projects a new dimension in the use of single phase MLIs for renewable energy related applications.