• Proceedings of the Korea Society for Simulation Conference
• /
• 1999.04a
• /
• pp.1-5
• /
• 1999

An ATM switch is the basic component of an ATM network, and its functioning is to switch incoming cells arriving at an input port to the output port associated with an appropriate virtual path. In case of an ATM switch with buffer sharing scheme, the performance analysis is very difficult due to the interactions between the address queues. In this paper, the influences of the degree of traffic burstiness and some traffic routing properties are investigated by using the simulation. Also, some cell access strategies including priority access and cell dropping are compared in terms of cell loss probability.

• Journal of Korea Multimedia Society
• /
• v.13 no.8
• /
• pp.1212-1220
• /
• 2010

The technologies of domestic user programs are not enough to convert address convert information, which was collected via port redirection server, to user traffic. Generally traffic redirection technology is a special purpose technology for I/O traffic via network device. L4 switch needs various additional costs and devices to achieve this special purpose. To solve this problem, there appears need for a central management of control and monitoring by centralizing traffic at one position regardless of network structure and it is necessary to realize redirection function of switch at network layer. Therefore this study offer development of traffic central control system through protocol redirection of client-side.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.24 no.8B
• /
• pp.1401-1411
• /
• 1999

Due to the increase of multimedia services, multicasting is considered as important design factor for ATM switch. To resolve the traffic expansion problem that is occurred by multicast in multistage interconnection networks, this paper proposes the multicast switch using a high-speed bus and a shared memory switch. Since the proposed switch uses a high-speed time division bus as a connection medium and chooses a shared memory switch as a basic switch module, it provides good port scalability. The traffic arbitration scheme enables internal non-blocking. By simulation we proves a good performance in the data throughput and the cell delay.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.1
• /
• pp.119-130
• /
• 1996

This paper is the part I of the full study about improved structure of fully interconnected ATM switch to develop the small sized switch element and practical implemention of switch network. This part I paper describes about proposed switch structure, performance evaluations and some of considerations to practical implementation. The proposed structure is constructed of two step buffering scheme in a filtered multiplexer. First step buffering is carried out by small sized dedicated buffers located at each input port. And second step buffering is provided by a large sized common buffer at the output port. To control bursty traffic, we use speed up factor in multiplexing and priority polling according to the levels of buffer occupancy. Proposed structure was evaluated by computer simulation with two evaluation points. One is comparision of multiplexing discipline between hub polling and priority polling. The ogher is overall which should be considered to improve the practical implementation.

• Proceedings of the Korean Institute of Communication Sciences Conference
• /
• 1991.10a
• /
• pp.137-140
• /
• 1991

The TDX-10 Time Switch architecture has modularity, high reliability and considerable large switch fabric having separated and both-way 1K time slot interchange switching circuit elements. In this paper, we present key functions, architecture, features and traffic characteristic of TDX-10 Time Switch. And we also describe some basic implementation technologies such as Frame Base Read-Write Separation Method, Multi-Write Method and Read-Write Separation Technique with Dual-port Memory.

• Proceedings of the Korean Information Science Society Conference
• /
• 1999.10c
• /
• pp.411-413
• /
• 1999

본 논문에선느 ATM 통신망을 위한 여러 ATM 스위치 모델들 중에서, 내부적으로 블록킹(blocking)이 없고 입출력 단에 각각 버퍼가 할당되어 있는 입출력 버퍼형 교환기에 대하여 연구하였다. 기존에서 스위치 스피드-업(Switch Speed-up) 기법하에서 주로 연구가 이루어졌다. 따라서, 본 논문에서는 유니폼 트래픽하에서 Output-port Expansion 기법을 사용한 귀환.손실 모드 및 하이브리드 모드하에서의 셀 손실률을 비교 분석하였다. Output-port Expansion 기법은, 한 타임 슬롯동안에 입력포트 당 하나의 셀만 교환되며, 만약 하나 이상의 셀들이 같은 출력포트로 향하면, 최대 교환되는 셀 수를 K(Output-port Expansion Ratio)개로 제한하는 방식이다. 유니폼 트래픽(uniform random traffic) 하에서 각 모드에 따른 셀 손실률을 비교 분석한 결과, 로드 0.9를 기점으로, 0.9이하의 로드에서는 하이브리드 모드가, 0.9이상의 로드에서는 손실모드가 가장 낮은 셀 손실률을 보인다.

• ETRI Journal
• /
• v.43 no.5
• /
• pp.799-811
• /
• 2021

This paper considers a challenging problem: to simultaneously optimize the cost and the quality of service in opaque wavelength division multiplexing (WDM) networks. An optimization problem is proposed that takes the information including network topology, traffic between end nodes, and the target level of congestion at each link/ node in WDM networks. The outputs of this problem include routing, link channel capacities, and the optimum number of switch ports locally added/dropped at all switch nodes. The total network cost is reduced to maintain a minimum congestion level on all links, which provides an efficient trade-off solution for the network design problem. The optimal information is utilized for dynamic traffic in WDM networks, which is shown to achieve the desired performance with the guaranteed quality of service in different networks. It was found that for an average link blocking probability equal to 0.015, the proposed model achieves a net channel gain in terms of wavelength channels (𝛾_w) equal to 35.72 %, 39.09 %, and 36.93 % compared to shortest path first routing and 𝛾_w equal to 29.41 %, 37.35 %, and 27.47 % compared to alternate routing in three different networks.

• The KIPS Transactions:PartC
• /
• v.9C no.4
• /
• pp.531-542
• /
• 2002

An input and output buffering ATM switch conventionally operates in either Queueloss mode or Backpressure mode. Recently, a new mode, which is called Hybrid mode, was proposed to overcome the drawbacks of Queueloss mode and Backpressure mode. In Hybrid mode, when both the destined output buffer and the originfted input buffer are full, a cell is dropped. This thesis analyzes the cell loss rate and the cell delay of Queueloss, Backpressure and Hybrid modes in a switch adopting output-port expansion scheme under uniform traffic. Output-port expansion scheme allows only one cell from an input buffer to be switched during one time slot. If several cells switch to a same destined output port, the number of maximum transfer cells is restricted to K (Output-port expansion ratio). The simulation results show that if an offered load is less than 0.9, Hybrid mode has lower cell loss rate than the other modes; otherwise, Queueloss mode illustrates the lowest cell loss rate, which is a different result from previous researches. However, the difference between Hybrid and Queueloss modes is comparably small. As expected, the average cell delay in Backpressure mode is lower than those of Queueloss mode and Hybrid mode, since the cell delay due to the retransmission of higher number of dropped cells in Backpressure mode is not considered.

• ETRI Journal
• /
• v.41 no.2
• /
• pp.197-206
• /
• 2019

Software-defined networking (SDN) is a modern approach for current computer and data networks. The increase in the number of business websites has resulted in an exponential growth in web traffic. To cope with the increased demands, multiple web servers with a front-end load balancer are widely used by organizations and businesses as a viable solution to improve the performance. In this paper, we propose a load-balancing mechanism for SDN. Our approach allocates web requests to each server according to its response time and the traffic volume of the corresponding switch port. The centralized SDN controller periodically collects this information to maintain an up-to-date view of the load distribution among the servers, and incoming user requests are redirected to the most appropriate server. The simulation results confirm the superiority of our approach compared to several other techniques. Compared to LBBSRT, round robin, and random selection methods, our mechanism improves the average response time by 19.58%, 33.94%, and 57.41%, respectively. Furthermore, the average improvement of throughput in comparison with these algorithms is 16.52%, 29.72%, and 58.27%, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.24 no.12A
• /
• pp.1922-1931
• /
• 1999

A multicast traffic’s feature is the function of providing a point to multipoints cell transmission, which is emerging from the main function of ATM switch. However, when a conventional point-to-point switch executes a multicast function, the excess load is occurred because unicast cell as well as multicast cell passed the copy network. Additionally, due to the excess load, multicast cells collide with other cells in a switch. Thus a deadlock that losses cells raises, extremely diminishes the performance of switch. An input queued switch also has a defect of the HOL (Head of Line) blocking that less lessens the performance of the switch. In the proposed multicast switch, we use shared memory switch to reduce HOL blocking and deadlock. In order to decrease switch’s complexity and cell's processing time, to improve a throughput, we utilize the method that routes a cell on a separated paths by traffic pattern and the scheduling algorithm that processes a maximum 2N cell at once in the control part. Besides, when cells is congested at an output port, a cell loss probability increases. Thus we use the Output Memory (OM) to reduce the cell loss probability. And we make use of the method that stores the assigned memory (UM, MM) with a cell by a traffic pattern and clears the cell of the Output memory after a fixed saving time to improve the memory utilization rate. The performance of the proposed switch is executed and compared with the conventional policy under the burst traffic condition through both the analysis based on Markov chain and simulation.