• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.3
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• pp.481-492
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• 1997

This paper presents an algorithm for recognizing surface mount device(SMD) IC pattern based on the error back propoagation(EBP) neural network and discrete cosine transform(DCT). In this approach, we chose such parameters as frequency, angle, translation and amplitude for the shape informantion of SMD IC, which are calculated from the coefficient matrix of DCT. These feature parameters are normalized and then used for the input vector of neural network which is capable of adapting the surroundings such as variation of illumination, arrangement of objects and translation. Learning of EBP neural network is carried out until maximum error of the output layer is less then 0.020 and consequently, after the learning of forty thousand times, the maximum error have got to this value. Experimental results show that the rate of recognition is 100% in case of the random pattern taken at a similar circumstance as well as normalized training pattern. It also show that proposed method is not only relatively relatively simple compare with the traditional space domain method in extracting the feature parameter but also able to re recognize the pattern's class, position, and existence.

• Transactions on Electrical and Electronic Materials
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• v.13 no.3
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• pp.129-135
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• 2012

A number of surface mount technology (SMT) process variables including land design are considered for minimizing tombstone defect in flexible printed circuit assembly in high volume manufacturing. As SMT chip components have been reduced over the past years with their weights in milligrams, the torque that once helped self-centering of chips, gears to tombstone defects. In this paper, we have investigated the correlation of the assembly process variables with respect to the tombstone defect by employing statistically designed experiment. After the statistical analysis is performed, we have setup hypotheses for the root causes of tombstone defect and derived main effects and interactions of the process parameters affecting the hypothesis. Based on the designed experiments, statistical analysis was performed to investigate significant process variable for the purpose of process control in flexible printed circuit manufacturing area. Finally, we provide beneficial suggestions for find-pitch PCB design, screen printing process, chip-mounting process, and reflow process to minimize the tombstone defects.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2453-2455
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• 2003

We propose a path planning method to reduce the inspection time of AOI (automatic optical inspection) machines in SMT (surface mount technology) in-line system. Inspection windows of board should be clustered to consider the FOV (field-of-view) of camera. The number of clusters is desirable to be minimized in order to reduce the overall inspection time. We newly propose a genetic algorithm to minimize the number of clusters for a given board. Comparative simulation results are presented to verify the usefulness of proposed algorithm.

• Journal of Korean Institute of Industrial Engineers
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• v.25 no.2
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• pp.204-216
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• 1999

Failure physics and statistical lifetime analysis constitute the two extreme ends of the reliability engineering spectrum, and studies that relate failure mechanisms to failure distributions have been near non-existent. This paper is an attempt to stimulate interest to fill the gap between the two extremes and proposes an approach of combining them through i) developing a failure mechanism model, ii) generating failure times by Monte Carlo simulation with the model, iii) deriving the failure time distribution and evaluating the product reliability, and iv) improving the product reliability by the sensitivity analysis. An application of the proposed approach to the BGA(Ball Grid Array) surface mount package is also provided.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.35-40
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• 2000

MCM technology languished troughout most of the 1990's due to high costs resulting from low yields and issues with known god die. During the last five years of the decade new developments in chip scale packages and high density, build up multi-layer printed wiring boards created new opportunities to design and produce ultra miniaturized modules using conventional surface mount manufacturing capabilities. Focus on the miniaturization of substrate based packages such as ball grid arrays (BGAs) resulted in chip scale packages (CSPs) offering many of the benefits of flip chip along with the handling, testing, manufacturing and reliability capabilities of packaged deviced. New developments in the PWB industry sought to reduce the size, weight, thickness and cost of high density interconnect (HDI) substrates. Shrinking geometries of vias and new constructions significantly increased the interconnect density available for MCM-L applications. This paper describes the most promising CSP and HDI technologies for portable products, high performance computing and dense multi-chip modules.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.12
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• pp.8306-8313
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• 2015

Open-type current sensors have been commonly used for DC motor controller, AC variable controller and Uninterruptible Power Supply. Recently they have begun to be used more widely, as the growth of renewable energy and smart-grid in power system. Considering most of the open-type current sensors are imported, developing the core technology needed to produce open-type current sensors is required. This paper describes the development and test results of open-type current sensors. Design of C type magnetic core, selection and test of a Hall sensor, design of current source circuit and signal conditioning circuit are described. 100A class DIP(Dual In-line Package) type and SMD(Surface Mount Devide) type open-type current sensors was made and tested. Test results show that the developed open-type current sensor satisfies the accuracy requirement of 2% and linearity requirement of 2% at 100 A of DC and AC current of 60Hz. Temperature compensation was carried out by using a temperature compensation circuit with NTC(Negative Temperature Coefficient) thermistor and the effect of the temperature compensation are described.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.28 no.3
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• pp.130-134
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• 2018

In the past few years, various solder compositions have been a representative material to electronic packages and surface mount technology industries as a replacement of Pb-base solder alloy. Therefore, extensive studies on process and/or reliability related with the low Ag composition have been reported because of recent rapid rise in Ag price. In this study, Sn-3.0Ag-0.5Cu, Sn-0.7Cu and Sn-0.3Ag-0.5Cu solder bar samples were fabricated by melting of Sn, Ag and Cu metal powders. Crystal structure and element concentration were analyzed by XRD, XRF, optical microscope, FE-SEM and EDS. The fabricated solder samples were composed of ${\beta}-Sn$, ${\varepsilon}-Ag_3Sn$ and ${\eta}-Cu_6Sn_5$ phases.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.11 s.114
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• pp.1112-1119
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• 2006

In this paper, mutually coupled oscillator is employed to improve phase noise. Mutually coupled structure oscillator couples two oscillator's phase shifted output signals, that is fabricated using teflon board which has dielectric constant of 2.5 and Surface Mount Gallium Arsenide FET devices. And this paper proposed the structure to bias adjustment for the phase condition of mutually couples. When one oscillator has bias point of 4.4 V and 37 mA, it's output signal has phase noise characteristic of -96.37 dBc(@9305 MHz, offset frequency 100 KHz), -73.46 dBc(10 kHz). and After it's output signal mutually coupled the other's output signal that has bias point of 8.1 V and 69 mA, it has superior phase noise characteristic of -106.7 dBc(@9305 MHz, offset frequency 100 kHz), -81 dBc(10 kHz).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.6
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• pp.481-486
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• 2010

ENIG (electroless Ni immersion gold) is one of surface finishing which has been most widely used in fine pitch SMT (surface mount technology) and BGA (ball grid array) packaging process. The reliability for package bondability is mainly affected by interfacial reaction between solder and surface finishing. Since the behavior of IMC (intermetallic compound), or the interfacial reaction between Ni and solder, affects to some product reliabilities such as solderability and bondability, understanding behavior of IMC should be important issue. Thus, we studied the properties of ENIG with P contents (9 wt% and 13 wt%), where the P contents is one of main factors in formation of IMC layer. The effect of P content was discussed using the results obtained from FE-SEM(field-emission scanning electron microscope), EPMA(electron probe micro analyzer), EDS(energy dispersive spectroscopy) and Dual-FIB(focused ion beam). Especially, we observed needle type irregular IMC layer with decreasing Ni contents under high P contents (13 wt%). Also, we found how IMC layer affects to bondability with forming continuous Kirkendall voids and thick P-rich layer.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2017.05a
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• pp.159-159
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• 2017

Ti-6Al-4V alloy have been used for dental implant because of its excellent biocompatibility, corrosion resistance, and mechanical properties. However, the integration of such implant in bone was not in good condition to achieve improved osseointergraiton. For solving this problem, calcium phosphate (CaP) has been applied as coating materials on Ti alloy implants for hard tissue applications because its chemical similarity to the inorganic component of human bone, capability of conducting bone formation and strong affinity to the surrounding bone tissue. Various metallic elements are known to play an important role in the bone formation and also affect bone mineral characteristics. Especially, Zn is essential for the growth of the human and Zn coating has a major impact on the improvement of corrosion resistance. Plasma electrolytic oxidation (PEO) is a promising technology to produce porous and firmly adherent inorganic Zn containing TiO2(Zn-TiO2)coatings on Ti surface, and the a mount of Zn introduced in to the coatings can be optimized by altering the electrolyte composition. In this study, effect of Zn content on the corrosion behavior of Ti-6Al-4V alloy after plasma electrolytic oxidation were studied by SEM, EDS, XRD, AC impedance, and potentiodynamic polarization test. The potentiodynamic polarization and AC impedance tests for corrosion behaviors were carried out in 0.9% NaCl solution at similar body temperature using a potentiostat with a scan rate of 1.67 mV/s and potential range from -1500 mV to +2000 mV. Also, AC impedance was performed at frequencies ranging from 10 MHz to 100 kHz for corrosion resistance.