• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.4
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• pp.475-483
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• 2012

This paper presents new type of the hybrid supply modulator for the next reconfigurable transmitters. The efficiency of the hybrid supply modulator is one of the most important performance. For enhancement the efficiency, multi-switching structure in the hybrid supply modulator is employed. Additionally, input envelope signal sensing stage is employed for implementation multi-mode operation. To compare the performance of the proposed hybrid supply modulator, the conventional hybrid supply modulator is also designed. The measured efficiency of the proposed hybrid supply modulator is 85 %/84 %/79 % for EDGE/WCDMA/LTE signals which have 384 kHz/3.84 MHz/5 MHz bandwidth, respectively. The efficiency of the proposed hybrid supply modulator is higher than the conventional hybrid supply modulator. Therefore, this structure shows good candidate for the reconfigurable transmitters.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.421-422
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• 2017

The kicker modulator was upgraded and installed in 1995. The PLS-II injection kicker modulator is configured with series resonant circuit. A total of four kicker magnets are used to distribute the normal storage ring beam orbit toward the septum magnet wall. Only one kicker modulator is used to drive the four kicker magnets. It is not adjust the current magnitude and timing of magnets. During the kicking, the beam has oscillation of 2 mm horizontal direction and $200{\mu}m$ vertical direction in present injector system. Our goals is to decrease the oscillation less than $300{\mu}m$. To give balanced current for all four magnets and to have precise timing between magnet current, we have plan to divide kicker power supply into four individual power supply. In this paper, the design of new individual kicker power supply and Fabrication of the new injector system is presented.

• Journal of IKEEE
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• v.22 no.4
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• pp.1019-1024
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• 2018

In this paper, we suggest a combined cost function to find out the optimal operation of an envelope tracking system, and evaluated its performance with Quadrature Amplitude Modulation (QAM) waveform, with which envelope tracking coefficients for the peak drain efficiency and the bandwidth of power amplifiers are determined. Based on the classical envelope tracking theory, the operation of the supply modulator, which is a key part of the envelope tracking process, is modeled and analyzed mathematically. Then characteristics of the modulator by setting envelope shaping function as a cubic polynomial and sweeping the coefficients of this function was analyzed. By sweeping the coefficients, efficiency and bandwidth at each condition with 64-QAM signal was used to obtain optimal point of the supply modulator. Compared to the conventional shaping functions, the optimized function showed the bandwidth reduction by 12.7 percent point while the efficiency was maintained.

• Journal of Power Electronics
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• v.5 no.4
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• pp.257-263
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• 2005

This paper describes the development and testing results of a high density High Voltage Power Supply (HVPS) that drives microwave Traveling Wave Tubes (TWTs) of phased array transmitters for airborne EW systems. The HVPS is designed to consist of a number of modules connected in series. Among them, especially, the high-density pulse transformer module including the resonant circuit is newly designed to make the HVPS much more reliable. In addition, this paper describes the development of high voltage solid-state modulation using fast switching devices (FETs) and also represents the test results of a modulator module.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.6
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• pp.1081-1086
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• 2008

This paper presents the $3^{rd}$ 4bit sigma delta modulator with the block and timing diagrams of DWA(Data Weighted Averaging) to optimize a operating time. In the modulator, the proposed DWA structure has a stable operation and timing margin so as to remove three latches and another clock. Because the modulator with proposed DWA structure improve timing margin about 23%. It can increase sampling frequency up to 244MHz. Through the MATLAB modeling, the optimized coefficients are obtained to design the modulator. The fully differential SC integrators, DAC, switch, quantizer, and DWA are designed by considering the nonideal characteristics. The designed $3^{rd}$ order 4bit modulator has a power consumption of 40mW and SNR(signal to noise ratio) of 77.2dB under 1.2V supply and 64MHz sampling frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1887-1894
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• 2010

This paper proposes a new switched-capacitor sigma-delta modulator for automotive radars. Developed modulator is used to perform high-resolution analog-to-digital conversion (ADC) of high frequency band signal in a radar system. It has supply voltage of 2.7V, and has body-effect compensated switch configuration with low voltage and low distortion. The modulator has been implemented in a $0.25{\mu}m$ double-poly and triple-metal standard CMOS process, and it has die area of $1.9{\times}1.5mm^{2}$. It showed better total harmonic distortion of 20dB than the conventional bootstrapped circuit at the supply voltage of 2.7V.

• Journal of Sensor Science and Technology
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• v.33 no.3
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• pp.147-151
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• 2024

The importance of Wireless Sensor Networks is becoming more evident owing to their practical applications in various areas. However, the energy problem remains a critical barrier to the progress of WSNs. By reducing the energy consumed by the sensor nodes that constitute WSNs, the performance and lifespan of WSNs will be enhanced. In this study, we introduce an energy-efficient ternary modulator that employs multi-threshold CMOS for logic conversion. We optimized the design with a low-power ternary gate structure based on a pass transistor using the MTCMOS process. Our design uses 71.69% fewer transistors compared to the previous design. To demonstrate the improvements in our design, we conducted the HSPICE simulation using a CMOS 180 nm process with a 1.8V supply voltage. The simulation results show that the proposed ternary modulator is more energy-efficient than the previous modulator. Power-delay product, a benchmark for energy efficiency, is reduced by 97.19%. Furthermore, corner simulations demonstrate that our modulator is stable against PVT variations.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.87-90
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• 2002

This paper describes design technique of switched-capacitor 1V delta-sigma modulator. To solve the incomplete switching operation at low voltage, bootstrapping technique is used. For PMOS input pair of 1V operational amplifier, simple common mode level down technique is used. Designed 2nd order single loop modulator has an oversampling ratio of 64 and obtains a peak SNR of 71dB, a dynamic range of 73 dB with the power consumption of 350uW at 1V power supply.

• Proceedings of the KIPE Conference
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• 2004.07a
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• pp.64-67
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• 2004

The klystron-modulator(K&M) system of the Pohang Light Source(PLS) had been supplying high power microwaves for the acceleration of 2.5 GeV electron beams since October 2002. There are 12 sets of K&M systems to accelerate electron beams to 2.5GeV nominal beam energy. One module of the K&M system consists of an 80 MV S-band (2856 MHZ) klystron tube and the matching 200 MW modulator. In order to obtain electron beam of the consequently stability for linac, the pulse-to-pulse beam voltage regulation is less than $+/-0.5\%$. To get the reliable stability of the modulator which is less than $+/-0.5\%$, a charging section is improved in a modulator which has been operated with inverter power supply.

• Journal of electromagnetic engineering and science
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• v.14 no.1
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• pp.1-8
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• 2014

A differential-cascode CMOS power amplifier (PA) with a supply modulator for envelope tracking (ET) has been implemented by 0.18 ${\mu}m$ RF CMOS technology. The loss at the output is minimized by implementing the output transformer on a FR-4 printed circuit board (PCB). The CMOS PA utilizes the $2^{nd}$ harmonic short at the input to enhance the linearity. The measurement was done by the 10MHz bandwidth 16QAM 6.88 dB peak-to-average power ratio long-term evolution (LTE) signal at 1.85 GHz. The ET operation of the CMOS PA with the supply modulator enhances the power-added efficiency (PAE) by 2.5, to 10% over the stand-alone CMOS PA for the LTE signal. The ET PA achieves a PAE of 36.5% and an $ACLR_{E-UTRA}$ of -32.7 dBc at an average output power of 27 dBm.