• Title/Summary/Keyword: Successive Channel Switching

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Uncoordinated Dynamic Frequency Allocation Schemes based on Cognitive Radio in Mobile Cellular Networks (이동셀룰러망에서 무선 인지 기반 비협력 동적 주파수 자원 할당 기법)

  • Yu, Hyun;Jung, Jun-Woo;Lee, Jong-Kwan;Lim, Jae-Sung
    • Journal of the Korea Institute of Military Science and Technology
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    • v.14 no.5
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    • pp.833-841
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    • 2011
  • In this paper, we propose uncoordinated dynamic frequency(channel) allocation schemes based on cognitive radio in mobile cellular networks(MCNs). Under the assumptions that mobile base stations are equipped with cognitive radio(CR) function and they construct uncoordinated network, the proposed scheme enables the MCNs by suppression of successive channel switching and management of channel allocation in a dynamic and distributed manner. The proposed scheme is composed of two phase processes. In the first phase, highly orthogonal sequences are generated and assigned to mobile base stations. In the second phase, each mobile base station is allocated a channel according to the pre-assigned orthogonal sequences. Simulation results show that the number of successive spectrum switching is reduced significantly compared with the random switching scheme.

A Single-Ended ADC with Split Dual-Capacitive-Array for Multi-Channel Systems

  • Cho, Seong-Jin;Kim, Ju Eon;Shin, Dong Ho;Yoon, Dong-Hyun;Jung, Dong-Kyu;Jeon, Hong Tae;Lee, Seok;Baek, Kwang-Hyun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.5
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    • pp.504-510
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    • 2015
  • This paper presents a power and area efficient SAR ADC for multi-channel near threshold-voltage (NTV) applications such as neural recording systems. This work proposes a split dual-capacitive-array (S-DCA) structure with shifted input range for ultra low-switching energy and architecture of multi-channel single-ended SAR ADC which employs only one comparator. In addition, the proposed ADC has the same amount of equivalent capacitance at two comparator inputs, which minimizes the kickback noise. Compared with conventional SAR ADC, this work reduces the total capacitance and switching energy by 84.8% and 91.3%, respectively.

8 Antenna Polar Switching Up-Down Relay Networks

  • Li, Jun;Lee, Moon-Ho;Yan, Yier;Peng, Bu Shi;Hwang, Gun-Joon
    • Journal of electromagnetic engineering and science
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    • v.11 no.4
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    • pp.239-249
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    • 2011
  • In this paper, we propose a reliable $8{\times}8$ up-down switching polar relay code based on 3GPP LTE standard, motivated by 3GPP LTE down link, which is 30 bps/Hz for $8{\times}8$ MIMO antennas, and by Arikan's channel polarization for the frequency selective fading (FSF) channels with the generator matrix $Q_8$. In this scheme, a polar encoder and OFDM modulator are implemented sequentially at both the source node and relay nodes, the time reversion and complex conjugation operations are separately implemented at each relay node, and the successive interference cancellation (SIC) decoder, together with the cyclic prefix (CP) removal, is performed at the destination node. Use of the scheme shows that decoding at the relay without any delay is not required, which results in a lower complexity. The numerical result shows that the system coded by polar codes has better performance than currently used designs.

An 8b 200MHz Time-Interleaved Subranging ADC With a New Reference Voltage Switching Scheme (새로운 기준 전압 인가 방법을 사용하는 8b 200MHz 시간 공유 서브레인징 ADC)

  • Moon, Jung-Woong;Yang, Hee-Suk;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.39 no.4
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    • pp.25-35
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    • 2002
  • This work describes an 8b 200MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double-channel architecture to increase system speed and a new reference voltage switching scheme to reduce settling time of the reference voltages and chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves linearity and settling time of the reference voltages simultaneously. The proposed sample- and-hold amplifier(SHA) is based on a highly linear common-drain amplifier and passive differential circuits to minimize power consumption and chip area with 8b accuracy and employs input dynamic common mode feedback circuits for high dynamic performance at a 200MHz sampling rate. A new encoding circuit in a coarse ADC simplifies the signal processing between the coarse ADC and two successive fine ADCs.