• Title/Summary/Keyword: Sub-threshold transistor

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Enhancing Electrical Properties of Sol-Gel Processed IGZO Thin-Film Transistors through Nitrogen Atmosphere Electron Beam Irradiation (질소분위기 전자빔 조사에 의한 졸-겔 IGZO 박막 트랜지스터의 전기적 특성 향상)

  • Jeeho Park;Young-Seok Song;Sukang Bae;Tae-Wook Kim
    • Journal of the Microelectronics and Packaging Society
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    • v.30 no.3
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    • pp.56-63
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    • 2023
  • In this paper, we studied the effect of electron beam irradiation on sol-gel indium-gallium-zinc oxide (IGZO) thin films under air and nitrogen atmosphere and carried out the electrical characterization of the s ol-gel IGZO thin film transistors (TFTs). To investigate the optical properties, crystalline structure and chemical state of the sol-gel IGZO thin films after electron beam irradiation, UV-Visible spectroscopy, X-ray diffraction (XRD), and X-ray photoelectron spectroscopy (XPS) were carried out. The sol-gel IGZO thin films exhibited over 80% transmittance in the visible range. The XRD analysis confirmed the amorphous nature of the sol-gel IGZO films regardless of electron beam irradiation. When electron beam irradiation was conducted in a nitrogen (N2) atmosphere, we observed an increased proportion of peaks related to M-O bonding contributed to the improved quality of the thin films. Sol-gel IGZO TFTs subjected to electron beam exposure in a nitrogen atmosphere exhibited enhanced electrical characteristics in terms of on/off ratio and electron mobility. In addition, the electrical parameters of the transistor (on/off ratio, threshold voltage, electron mobility, subthreshold swing) remained relatively stable over time, indicating that the electron beam exposure process in a nitrogen atmosphere could enhance the reliability of IGZO-based thin-film transistors in the fabrication of sol-gel processed TFTs.

Interface Treatment Effect of High Performance Flexible Organic Thin Film Transistor (OTFT) Using PVP Gate Dielectric in Low Temperature (저온 공정 PVP게이트 절연체를 이용한 고성능 플렉서블 유기박막 트랜지스터의 계면처리 효과)

  • Yun, Ho-Jin;Baek, Kyu-Ha;Shin, Hong-Sik;Lee, Ga-Won;Lee, Hi-Deok;Do, Lee-Mi
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.24 no.1
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    • pp.12-16
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    • 2011
  • In this study, we fabricated the flexible pentacene TFTs with the polymer gate dielectric and contact printing method by using the silver nano particle ink as a source/drain material on plastic substrate. In this experiment, to lower the cross-linking temperature of the PVP gate dielectric, UV-Ozone treatment has been used and the process temperature is lowered to $90^{\circ}C$ and the surface is optimized by various treatment to improve device characteristics. We tried various surface treatments; $O_2$ Plasma, hexamethyl-disilazane (HMDS) and octadecyltrichlorosilane (OTS) treatment methods of gate dielectric/semiconductor interface, which reduces trap states such as -OH group and grain boundary in order to improve the OTFTs properties. The optimized OTFT shows the device performance with field effect mobility, on/off current ratio, and the sub-threshold slope were extracted as $0.63cm^2 V^{-1}s^{-1}$, $1.7{\times}10^{-6}$, and of 0.75 V/decade, respectively.

Effects of Interfacial Dielectric Layers on the Electrical Performance of Top-Gate In-Ga-Zn-Oxide Thin-Film Transistors

  • Cheong, Woo-Seok;Lee, Jeong-Min;Lee, Jong-Ho;KoPark, Sang-Hee;Yoon, Sung-Min;Byun, Chun-Won;Yang, Shin-Hyuk;Chung, Sung-Mook;Cho, Kyoung-Ik;Hwang, Chi-Sun
    • ETRI Journal
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    • v.31 no.6
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    • pp.660-666
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    • 2009
  • We investigate the effects of interfacial dielectric layers (IDLs) on the electrical properties of top-gate In-Ga-Zn-oxide (IGZO) thin film transistors (TFTs) fabricated at low temperatures below $200^{\circ}C$, using a target composition of In:Ga:Zn = 2:1:2 (atomic ratio). Using four types of TFT structures combined with such dielectric materials as $Si_3N_4$ and $Al_2O_3$, the electrical properties are analyzed. After post-annealing at $200^{\circ}C$ for 1 hour in an $O_2$ ambient, the sub-threshold swing is improved in all TFT types, which indicates a reduction of the interfacial trap sites. During negative-bias stress tests on TFTs with a $Si_3N_4$ IDL, the degradation sources are closely related to unstable bond states, such as Si-based broken bonds and hydrogen-based bonds. From constant-current stress tests of $I_d$ = 3 ${\mu}A$, an IGZO-TFT with heat-treated $Si_3N_4$ IDL shows a good stability performance, which is attributed to the compensation effect of the original charge-injection and electron-trapping behavior.

Dependence of $O_2$ Plasma Treatment of Cross-Linked PVP Insulator on the Electrical Properties of Organic-Inorganic Thin Film Transistors with ZnO Channel Layer

  • Gong, Su-Cheol;Shin, Ik-Sup;Bang, Suk-Hwan;Kim, Hyun-Chul;Ryu, Sang-Ouk;Jeon, Hyeong-Tag;Park, Hyung-Ho;Yu, Chong-Hee;Chang, Ho-Jung
    • Journal of the Microelectronics and Packaging Society
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    • v.16 no.2
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    • pp.21-25
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    • 2009
  • The organic-inorganic thin film transistors (OITFTs) with ZnO channel layer and the cross-linked PVP (Poly-4-vinylphenol) gate insulator were fabricated on the patterned ITO gate/glass substrate. ZnO channel layer was deposited by using atomic layer deposition (ALD). In order to improve the electrical properties, $O_2$ plasma treatment onto PVP film was introduced and investigated the effect of the plasma treatments on the electrical properties of the OITFTs. The field effect mobility and sub-threshold slope (SS) values of the OITFT decreased slightly from 0.24 to 0.16 $cm^2/V{\cdot}s$ and from 9.7 to 9.2 V/dec, respectively with increasing RF power from 30 to 50 Watt. The $I_{on/off}$ ratio was about $10^3$ for all samples with $O_2$ plasma treatment.

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Improved Degradation Characteristics in n-TFT of Novel Structure using Hydrogenated Poly-Silicon under Low Temperature (낮은 온도 하에서 수소처리 시킨 다결정 실리콘을 사용한 새로운 구조의 n-TFT에서 개선된 열화특성)

  • Song, Jae-Ryul;Lee, Jong-Hyung;Han, Dae-Hyun;Lee, Yong-Jae
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2008.05a
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    • pp.105-110
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    • 2008
  • We have proposed a new structure of poly-silicon thin film transistor(TFT) which was fabricated the LDD region using doping oxide with graded spacer by etching shape retio. The devices of n-channel poly-si TFT's hydrogenated by $H_2$ and $HT_2$/plasma processes are fabricated for the devices reliability. We have biased the devices under the gate voltage stress conditions of maximum leakage current. The parametric characteristics caused by gate voltage stress conditions in hydrogenated devices are investigated by measuring /analyzing the drain current, leakage current, threshold voltage($V_{th}$), sub-threshold slope(S) and transconductance($G_m$) values. As a analyzed results of characteristics parameters, the degradation characteristics in hydrogenated n-channel polysilicon TFT's are mainly caused by the enhancement of dangling bonds at the poly-Si/$SiO_2$ interface and the poly-Si Brain boundary due to dissolution of Si-H bonds. The structure of novel proposed poly-Si TFT's are the simplity of the fabrication process steps and the decrease of leakage current by reduced lateral electric field near the drain region.

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