• Journal of the Korean Electrochemical Society
• /
• v.12 no.1
• /
• pp.47-53
• /
• 2009

In this study, highly ordered AAO (Anodic Aluminum Oxide) with nanopores was prepared by commercial grade Al substrate containing 3.5 wt.% impurities through two step anodizing method. Nanopores of prepared AAO arrays were used as templates for preparing nanofiber. $TiO_2$ was deposited by using DP (deposition-precipitation) method into AAO pores to grow nanofiber. Au particles were loaded on this $TiO_2$ nanofiber which was grown vertically. Prepared 2 wt.% $Au/TiO_2$ nanofiber was characterized by XRD, SEM and Raman. The crystal structure was analyzed by the XRD. SEM was used to observe pore size and pore wall thickness. Photocatalytic activity of co-oxidation was compared with $TiO_2$ and $Au/TiO_2$ nanofiber on AAO arrays.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.16 no.6
• /
• pp.509-518
• /
• 2023

In this paper, we designed a 4Kb poly-fuse OTP IP (Intellectual Property) required for analog circuit trimming and calibration. In order to reduce the BL resistance of the poly-fuse OTP cell, which consists of an NMOS select transistor and a poly-fuse link, the BL stacked metal 2 and metal 3. In order to reduce BL routing resistance, the 4Kb cells are divided into two sub-block cell arrays of 64 rows × 32 rows, with the BL drive circuit located between the two 2Kb sub-block cell arrays, which are split into top and bottom. On the other hand, in this paper, we propose a core circuit for an OTP cell that uses one poly-fuse link to one select transistor. In addition, in the early stages of OTP IP development, we proposed a data sensing circuit that considers the case where the resistance of the unprogrammed poly-fuse can be up to 5kΩ. It also reduces the current flowing through an unprogrammed poly-fuse link in read mode to 138㎂ or less. The poly-fuse OTP cell size designed with DB HiTek 90nm CMOS process is 11.43㎛ × 2.88㎛ (=32.9184㎛2), and the 4Kb poly-fuse OTP IP size is 432.442㎛ × 524.6㎛ (=0.227mm²).

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.2
• /
• pp.108-113
• /
• 2013

This paper describes a low power asynchronous successive approximation register (SAR) type 12b analog-to-digital converter (ADC) for biomedical applications in a 0.35 ${\mu}m$ CMOS technology. The digital-to-analog converter (DAC) uses a capacitive split-arrays consisting of 6-b main array, an attenuation capacitor C and a 5-b sub array for low power consumption and small die area. Moreover, splitting the MSB capacitor into sub-capacitors and an asynchronous SAR reduce power consumption. The measurement results show that the proposed ADC achieved the SNDR of 68.32 dB, the SFDR of 79 dB, and the ENOB (effective number of bits) of 11.05 bits. The measured INL and DNL were 1.9LSB and 1.5LSB, respectively. The power consumption including all the digital circuits is 6.7 ${\mu}W$ at the sampling frequency of 100 KHz under 3.3 V supply voltage and the FoM (figure of merit) is 49 fJ/conversion-step.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.30 no.3
• /
• pp.202-208
• /
• 2019

In this study, an active element pattern (AEP) of a printed dipole was analyzed in 1D and 2D arrays. First, an AEP of the printed dipole was obtained using the simulation in the 2D infinite array. The scan blindness in the 2D array occurred in the E-plane direction at around ${\pm}36^{\circ}$; however, it was barely observed in the 1D array. To analyze the cause of the scan blindness in the 2D array, the dispersion properties of a unit cell was obtained and compared with the scan blindness by frequency change. The difference between the scan blindness of the 1D and 2D arrays was clarified using the comparison of the Q value in the unit cell in the 1D and 2D arrays. Then, the coupling of the electric field in the E-plane direction was observed when nine elements were separated between the two ports in a linearly arranged dipole structure. Finally, the printed dipole array was fabricated, and an AEP was measured for the $11{\times}1$ and $11{\times}3$ sub arrays. The proposed theory was verified using these observations and by comparison with the simulation results.

• Nano
• /
• v.13 no.11
• /
• pp.1850125.1-1850125.12
• /
• 2018

To reduce the imbalance of impedance matching between the magnetic metal nanowires and free space, $Fe/TiO_2$ core/shell nanowire arrays with different diameters were fabricated in the templates of anodic aluminum oxide membranes by electrodeposition. The influences of the microstructure on the microwave absorption properties of the $Fe/TiO_2/Al_2O_3$ composites were studied by the transmission/reflection waveguide method. It was demonstrated experimentally that both the interfacial polarization and the diameter of the $Fe/TiO_2$ core/shell nanowires have critical effects on the microwave absorption properties. We also investigated the angle dependence of the microwave absorption properties. Due to the interfacial polarization and associated relaxation, the $Fe/TiO_2/Al_2O_3$ composites exhibited optimal microwave absorption properties when microwave propagation direction was accordant with the axis of the nanowires. Finally, we managed to obtain an optimal reflection loss of below -10 dB (90% absorption) over 10.2-14.8 GHz, with a thickness of 3.0 mm and the minimum value of -39.4 dB at 11.7 GHz.

• Journal of the Korean Ceramic Society
• /
• v.39 no.6
• /
• pp.582-588
• /
• 2002

IrO$_2$-RuO$_2$ films were deposited on plasma sprayed TiO$_2$ buffer layer above Ti metal by sol-gel and dip-coating method. Organic vehicle (ethyl cellulose and $\alpha$-terpineol) and glass frit were added to improve adherence of the coatings. Taguchi method and L$_{18}$ (2$^1$$\times$3$^{7}$ ) orthogonal arrays were evalvated in terms of current density to determine the optimal combination of levels of factors that best satisfy the bigger is better quality characteristic. The observed conditions were as fellows: ethyl cellulose (100 cp), drying temperature and time (17$0^{\circ}C$,20 min), heat treatment temperature and time (75$0^{\circ}C$,10 min), the weight ratio of IrO$_2$-RuO/powders to glass frit (99:5), final heat treatment time (120 min) and flow rate of air (5 sccm), respectively. ANOVA analysis suggested that the influence of the factors within $\alpha$= 0.1 was significant with a 90% confidence level.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.24 no.3
• /
• pp.14-19
• /
• 2010

Partial anodic oxidation of Ti-mesh with a wire diameter of ~200[${\mu}m$] produces self-aligned $TiO_2$ nanotube arrays (~50[${\mu}m$] in length) on Ti-mesh substrate. The electrolyte used for anodic oxidation was an ethylene glycol solution with an addition of 1.5 vol. % $H_2O$ and 0.2 wt. % $NH_4F$. A dye-sensitized solar cell utilizing the photoanode structure of $TiO_2$-nanotube/Ti-mesh was fabricated without a transparent conducting oxide (TCO) layer, in which Ti-mesh replaced the role of TCO. The 1.93[%] photoconversion efficiency was low, which can be attributed to both insufficient dye molecules attachment and limited electrolyte flow to dye molecules. The optimized nanotube diameter and length as well as the $TiCl_4$ treatment can improve cell performance.

• Current Photovoltaic Research
• /
• v.1 no.1
• /
• pp.69-72
• /
• 2013

Combined nano- and micro-wires (CNMWs) Si arrays were prepared using PR patterning and silver-assisted electroless etching. A $POCl_3$ doping process was applied to the fabrication of CNMWs solar cells. KOH solution was used to remove bundles in CNMWs and the etching time was varied from 30 to 240 s. The lowest reflectance of 3.83% was obtained at KOH etching time of 30 s, but the highest carrier lifetime of $354{\mu}s$ was observed after the doping process at 60 s. At the same etching time, a $V_{oc}$ of 574 mV, $J_{sc}$ of $28.41mA/cm^2$, FF of 74.4%, and Eff. of 12.2% were achieved in the CNMWs solar cell. CNMWs solar cells have potential for higher efficiency by improving the post-process and surface-rear side structure.

• Journal of Digital Contents Society
• /
• v.18 no.3
• /
• pp.613-619
• /
• 2017

This paper presents a CUDA (Compute Unified Device Architecture) code to achieve correct GPU parallel segmented prefix operation results with less than 32 segment length for large data arrays. Mark Harris and Michael Garland had published CUDA code to address the tasks. This paper shows that their code does not generate correct results when the local segment length is less than 32, discusses the cause of the problem, and presents a CUDA code that generates correct results. The segmented parallel prefix operation presented in this paper can be applied as a building block to various large parallel processing algorithms including the k-nearest neighbor search problems.

• Journal of the Korean Society for Precision Engineering
• /
• v.28 no.12
• /
• pp.1419-1424
• /
• 2011

Nanoimprint lithography is a next generation lithography technology, which enables to fabricate nano to micron-scale patterns through simple and low cost process. Nanoimprint lithography has been applied in various industry fields such as light emitting diodes, solar cells and display. Functional patterns, including anti-reflection moth-eye pattern, photonic crystal pattern, fabricated by nanoimprint lithography are used to improve overall efficiency of devices in that fields. For these reasons, in this study, sub-micron-scaled functional patterns were directly fabricated on Si and glass substrates by thermal imprinting process using ZnO nano-particles dispersion resin. Through the thermal imprinting process, arrays of sub-micron-scaled pillar and hole patterns were successfully fabricated on the Si and glass substrates. And then, the topography, components and optical property of the imprinted ZnO nano-particles/resin patterns are characterized by Scanning Electron Microscope, Energy-dispersive X-ray spectroscopy and UV-vis spectrometer, respectively.