• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.855-858
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• 2001

The stress induced leakage currents of thin silicon oxides is investigated in the VLSI implementation of a self learning neural network integrated circuits using a linearity synapse transistor. The channel current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 41 ${\AA}$, 86${\AA}$, which have the channel width ${\times}$ length 10 ${\times}$1${\mu}$m, 10 ${\times}$0.3${\mu}$m respectively. The stress induced leakage currents will affect data retention in synapse transistors and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses. The synapse transistor made by thin silicon oxides has represented the neural states and the manipulation which gaves unipolar weights. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the channel current. The stress induced leakage currents affected excitatory state and inhitory state.

• Proceedings of the IEEK Conference
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• summer
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• pp.209-212
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• 2004

In this paper, The stress induced leakage currents of thin silicon oxides is investigated in the nano scale structure implementation for Soc. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The channel current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $41\square\;and\;113.4\square,$ which have the channel width x length 10x1um, respectively. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the channel current. The stress induced leakage currents affected excitatory state and inhitory state.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.889-893
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• 2015

In this work, the characteristics of GIDL current in nanowire GAA MOSFET with different channel width and hot carrier stress. When the gate length is fixed as a 250nm the GIDL current with different channel width of 10nm, 50nm, 80nm, and 130nm have been measured and analyzed. From the measurement, the GIDL is increased as the channel width decreaes. However, the derive current is increased as the channel width increases. From measurement results after hot carrier stress, the variation of GIDL current is increased with decreasing channel width. Finally, the reasons for the increase of GIDL current with decreasing channel width and r device. according to hot carrier stress GIDL's variation shows big change when width and the increase of GIDL current after hot carrier stress are confirmed through the device simulation.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.285-291
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• 2013

In this paper, MOS-Capacitor and MOSFET devices with a Low Level Leakage Current of oxide thickness, channel width and length respectively were to investigate the reliability characterizations mechanism of ultra thin gate oxide films. These stress induced leakage current means leakage current caused by stress voltage. The low level leakage current in stress and transient current of thin silicon oxide films during and after low voltage has been studied from strss bias condition respectively. The stress channel currents through an oxide measured during application of constant gate voltage and the transient channel currents through the oxide measured after application of constant gate voltage. The study have been the determination of the physical processes taking place in the oxides during the low level leakage current in stress and transient current by stress bias and the use of the knowledge of the physical processes for driving operation reliability.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1101-1104
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• 2003

In this paper, we analyzed the gate current and substrate current by the hot carrier effects and restoration phenomenon of characteristics by time in the p-channel MOSFETs. The Stress voltage condition is a voltage in maximum gate current and time is 3s, 10s, 30s, l00s, 1000s, 2000s and 3000s. As results of analysis, the gate current and substrate current were decreased by stress time, and the restoration time of characteristics were shown the results that were decreased by the exponential times.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.2
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• pp.122-129
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• 2015

In this study, we propose a low voltage stress and cost-effective light emitting diode (LED) driver capable of multi-channel current balancing. Conventional LED drivers require as many boost converters as the number of LED channels, whereas the proposed LED driver requires only one buck converter and several balancing capacitors instead of several expensive boost converters. Additionally, while the components of the boost converter have high voltage stress and depend on the LED driving voltage, components of the proposed driver have about one-half of the voltage stress across all components. The proposed driver exhibits high reliability and cost effectiveness because it only uses few DC blocking capacitors with no additional active devices to balance the current of multi-channel LEDs. The proposed driver exhibits high reliability and cost effectiveness. The validity of the proposed driver is confirmed through a theoretical analysis. An explanation of the design considerations and experimental results were obtained using a prototype applicable to a 46" LED-TV.

• Electrical & Electronic Materials
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• v.10 no.8
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• pp.783-793
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• 1997

A VLSI implementation of a self-learning neural network integrated circuits using a linearity synapse transistor is investigated. The thickness dependence of oxide current density stress current transient current and channel current has been measured in oxides with thicknesses between 41 and 112 $\AA$, which have the channel width $\times$ length 10 $\times$1${\mu}{\textrm}{m}$, 10 $\times$ 0.3${\mu}{\textrm}{m}$ respectively. The transient current will affect data retention in synapse transistors and the stress current is used to estimate to fundamental limitations on oxide thicknesses. The synapse transistor has represented the neural states and the manipulation which gaves unipolar weights. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the drain source current.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.59-62
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• 2000

A VLSI implementation of a self-learning neural network integrated circuits using a linearity synapse transistor is investigated. The thickness dependence of oxide current density, stress current, transient current and channel current has been measured in oxides with thicknesses between 41 and 112 $\AA$, which have the channel width$\times$length 10$\times$1${\mu}{\textrm}{m}$ respectively. The transient current will affect data retention in synapse transistors and the stress current is used to estimate to fundamental limitations on oxide thicknesses. The synapse transistor has represented the neural states and the manipulation which gave unipolar weights. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the drain source current.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.7
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• pp.780-790
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• 1988

We have studied the hot-carrier-induced degradation caused by the high channel electric field due to the decrease of the gate length of MOSFET used in VLSI. Under DC stress, the condition in which maximum substrate current occures gave the worst degradation. Under AC dynamic stress, other conditions, the pulse shape and the falling rate, gave enormous effects on the degradation phenomena, especially at 77K. Threshold voltage, transconductance, channel conductance and gate current were measured and compared under various stress conditions. The threshold voltage was almost completely recovered by hot-injection stress as a reverse-stress. But, the transconductance was rapidly degraded under hot-hole injection and recovered by sequential hot-electron stress. The Si-SiO2 interface state density was analyzed by a charge pumping technique and the charge pumping current showed the same trend as the threshold voltage shift in degradation process.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.145-148
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• 2001

In this paper, polycrystalline silicon thin film transistor using by Solid Phase Crystallization(SPC) were fabricated, and these devices were measured and analyzed the electrical output and transfer characteristics along to DC voltage stress. The transfer characteristics of polycrystalline silicon thin film transistor depended on drain and gate voltages. Threshold voltage is high with long channel length and narrow channel width. And output characteristics of polycrystalline silicon thin film transistor flowed abruptly much higher drain current. The devices induced electrical stress are decreased drain current. At last, field effect mobility is the faster as channel length is high and channel width is narrow.