• Tribology and Lubricants
• /
• v.5 no.2
• /
• pp.68-76
• /
• 1989

In this paper, the influence of ram-pressure on the static and dynamic characteristics of infinite width tilting-pad journal bearing is investigated theoretically. The ram-pressure is obtained by assumption of conservation of mechanical energy of the lubricant flow through the leading edge of the pad. The pressure in the lubricating film is numerically calculated using the ram-pressure obtained as the inlet pressure boundary condition of the pad. The static equilibrium state of tilting-pad journal bearing is determined by Newton-Raphson iteration method. A numerical results are presented in graphic form and relationships between the ram-pressure and the static and dynamic characteristics are discussed.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.659-660
• /
• 2006

The low crosstalk row-decoder is studied for PoRAM applications. Because polymer-based memories can be more densely integrated than established silicon-based ones, PoRAM is highly sensitive for the crosstalk problem. To overcome the problem and to suggest the suitable decoder for PoRAM, this paper shows the comparison of the row-path characteristics for both the 2-stage dynamic logic decoder and the 2-stage static logic decoder. Moreover, to suppress the Glitch effect which is observed by using the static logic decoder, the Master-Slave(M/S) D-Flip/Flop(D-F/F) is applied as a deglitch. Finally, the improved output result of the 2-stage static logic decoder with the M/S D-F/F is shown..

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.55 no.4
• /
• pp.199-203
• /
• 2006

This paper presents an ASER (Accelerated Soft Error Rate) integral model. The model is based on the facts that the generated EHP/s(electron hole pairs) are diminished after some residual range of the incident alpha particle, where residual range is a function of the incident angle and the capping layer thickness over the semiconductor junction. The ASER is influenced by the flux of the alpha particles, the junction area ratio, the alpha particle incident angle when the critical charge is same as the collected charge, and the sizes of the alpha source and the chip. The model was examined with 8M static RAM samples. The measured ASER data showed good agreement with the calculated values using the model. The ASER decreased exponentially with respect to the operational voltage. As the capping layer thickness increases up to $16{\mu}m$, the ASER increases, and after that thickness, the ASER decreases. The ASER increased as the depth of BNW increased from $0{\mu}m\;to\;4{\mu}m$. and then saturated. The ASER decreased as the node capacitance increased from 2fF to 5fF.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.35 no.6B
• /
• pp.948-953
• /
• 2010

In this paper, we propose multi-bit soft error detection method which can use an instruction cache of superscalar CPU architecture. Proposed method is applied to high-speed static RAM for instruction cache. Using 1D parity and interleaving, it has less memory overhead and detects more multi-bit errors comparing with other methods. It only detects occurrence of soft errors in static RAM. Error correction is treated like a cache miss situation. When soft errors are occurred, it is detected by 1D parity. Instruction cache just fetch the words from lower-level memory to correct errors. This method can detect multi-bit errors in maximum 4$\times$4 window.

• International Journal of Reliability and Applications
• /
• v.2 no.4
• /
• pp.269-280
• /
• 2001

The objective of this paper is to provide a model for effective implementation of costing RAM management in the design and procurement of production facility considering the system cost-performance trade-off. This research proposes a two-step approach of costing RAM design and test of system RAM for production facility. In Step 1, a static model is proposed to find an initial system configuration to meet the required performance based on system RAM and LCC and analyzes the trade-off relationships between various factors of RAM and LCC. In the second Step, we developed time and failure truncated models for system reliability test and analysis. For the computational purpose, we developed computer programs and have shown the sample results. By the sample test run, the proposed model has shown the possibilities to provide a good method to analyze system performance evaluation for both design and operational phase, This model can be applied to a wide variety of systems not only for costing RAM of the production facilities but also for the other kinds of equipment.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.55 no.3
• /
• pp.111-115
• /
• 2006

We investigated accelerated soft error rate(ASER) in 8M static random access memory(SRAM) cells. The effects on ASER by well structure, operational voltage, and cell transistor threshold voltage are examined. The ASER decreased exponentially with respect to operational voltage. The chips with buried nwell1 layer showed lower ASER than those either with normal well structure or with buried nwell1 + buried pwell structure. The ASER decreased as the ion implantation energy onto buried nwell1 changed from 1.5 MeV to 1.0 MeV. The lower viscosity of the capping layer also revealed lower ASER value. The decrease in the threshold voltage of driver or load transistor in SRAM cells caused the increase in the transistor on-current, resulting in lower ASER value. We confirmed that in order to obtain low ASER SRAM cells, it is necessary to also the buried nwell1 structure scheme and to fabricate the cell transistors with low threshold voltage and high on-current.

• Journal of Korean Electronics
• /
• v.7 no.12
• /
• pp.50-55
• /
• 1987

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1996.11a
• /
• pp.23-25
• /
• 1996

In this paper aims at studying the minimal test pattem of the RAM. This also propose a scheme of testing faults from the new fault model using the LLB. The length of test patterns are 6N(1-wsf), 9.5N(2-wsf), 7N(3-wsfl, 3N(4-wsf) operations in N-bit RAM. This test techniques can write into memory cell the number of write operations is reduced and then much testing time is saved. A test set which detects all positive-negative static t-ws faults for t=0, 1, 2, 3, 4 and detects all pattern sensitive fault in memory array. A new fault model, which encompasses the existing fault model Is proposed.

• Proceedings of the KIEE Conference
• /
• 1993.07b
• /
• pp.1206-1208
• /
• 1993

This paper is to study and realize a measuring device for complex dielectric constants. The device is consisted in order of interface unit, external RAM, programmable counter, D/A converter, measuring circuit, Sample & Hold circuit, A/D converter and related control circuits. Various excitation waves are digitalized and sent to the 4096 static RAM by personal computer. These data saved in the RAM are converted to analog excitation waves through D/A converter. The frequency of excitation wave is depend on the read-out speed of the RAM according to clock pulses. Such generated waves are applied to dielectrics under test and their responses are sampled and converted to digital data through A/D converter. The computer takes the digital data and calculates finally the complex dielectric constants. The frequencies for Measurement ranges from 0.04 Hz to 10 kHz.

• Proceedings of the KSR Conference
• /
• 2011.10a
• /
• pp.2493-2502
• /
• 2011

For Static analysis of software code, an experienced tester prefer detecting defects with using selective static technique. Many cases of static method have been reported such as coding rules, software metrics, defect data, etc. However, many of analysis case only present effectiveness of static analysis, not enough description for how the tester judged to classify code defects used in code analysis and removed them properly for ensure high quality. Occasionally, there are materials to show the effect of through some examples through some examples. But difficult to gain trust, because of not enough detail for application process. In this paper, introduced the static technique commonly used in railway and applied to the real development challenges. And the each of results were compared and analyzed. It is hard to generalize the results of this parer. But can be used and referenced as a case of study.