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Radiation-Induced Soft Error Detection Method for High Speed SRAM Instruction Cache  

Kwon, Soon-Gyu (성균관대학교 정보통신공학부)
Choi, Hyun-Suk (성균관대학교 정보통신공학부)
Park, Jong-Kang (성균관대학교 정보통신공학부)
Kim, Jong-Tae (성균관대학교 정보통신공학부)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.35, no.6B, 2010 , pp. 948-953 More about this Journal
Abstract
In this paper, we propose multi-bit soft error detection method which can use an instruction cache of superscalar CPU architecture. Proposed method is applied to high-speed static RAM for instruction cache. Using 1D parity and interleaving, it has less memory overhead and detects more multi-bit errors comparing with other methods. It only detects occurrence of soft errors in static RAM. Error correction is treated like a cache miss situation. When soft errors are occurred, it is detected by 1D parity. Instruction cache just fetch the words from lower-level memory to correct errors. This method can detect multi-bit errors in maximum 4$\times$4 window.
Keywords
Soft Error; Instruction Cache; Static Ram; Interleaving; Burst Error;
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