• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.2
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• pp.254-259
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• 1987

This paper describes the CMOS standard cell library implemented in double metal single poly gate process with 3\ulcornerm design rule, and its results of testing. This standard cell library contains total 33 cells of random logic gates, flip-flop gates and input/output buffers. All of cell was made to have the equal height of 98\ulcornerm, and width in multiple constant grid of 9 \ulcornerm. For cell data base, the electric characteristics of each cell is investigated and delay is characterized in terms of fanout. As the testing results of Ring Oscillator among the cell library, the average delay time for Inverter is 1.05 (ns), and the delay time due to channel routing metal is 0.65(ps)per unit length.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.1
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• pp.68-74
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• 1985

In this Paper, we present a non-doglegging channel routing system for If layout using standard cells. This system produces a final two-layer wiring pattern in the horizontal track between two rows, each of which is a linear placement of standard cells of identical heights, satisfying the given net list specification. The layout of CMOS cell library Including nine primitive cells used in this paper is represented in CIF (Caltech Intermediate Form) using λ(Lambda) of 2 microns in Mead-Conway layout representation scheme. The cell dimension and 1/0 characteristics such as name, position and layer type of the pins are stored in Component Library to be used in the channel routing progranl, CROUT. 4 subprogram, NET-PLOT, was used to report a schemdtic layout result, and another subprogram, NETCIF was used to with a full-fledged final layout representation in GIF, A test run for realizing a dynamicmaster-slave D flip-flop with set/reset using primitive cells was shown to take 4 CPU seconds on VAX 11/780.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.74-78
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• 2006

This paper presents a high-speed pulse-based flip-flop with pseudo MUX-type scan compatible with the conventional master-slave flip-flop with MUX-type scan. The proposed flip-flop was implemented as the standard cell library using Samsung 130nm HS technology. The data-to-output delay and power-delay-product of the proposed flip-flop are reduced by up to 59% and 49%, respectively. By using this flop-flop, ARM11 softcore has achieved the maximum 1GHz operating speed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.407-410
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• 1999

Viterbi decoder is implemented with a Radix-4 architecture at 0.5$\mu\textrm{m}$ process even though the delay time of standard tell is big and it causes a bigger chip size. As process develops, the delay time of standard cells is getting smaller. Therefore, the requirement of speed and chip size is satisfied by using Radix-2 algorithm to implement Viterbi decoder.

• Journal of information and communication convergence engineering
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• v.20 no.2
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• pp.137-142
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• 2022

Monolithic three-dimensional (M3D) logics such as M3D-NAND, M3D-NOR, M3D-buffer, M3D 2×1 multiplexer, and M3D D flip-flop, consisting of modularized M3D inverters (M3D-INVs), have been proposed. In the previous M3D logic, each M3D logic had to be designed separately for a standard cell library. The proposed M3D logic is designed by placing modularized M3D-INVs and connecting interconnects such as metal lines or monolithic inter-tier-vias between M3D-INVs. The electrical characteristics of the previous and proposed M3D logics were simulated using the technology computer-aided design and Simulation Program with Integrated Circuit Emphasis with the extracted parameters of the previously developed LETI-UTSOI MOSFET model for n- and p-type MOSFETs and the extracted external capacitances. The area, propagation delay, falling/rising times, and dynamic power consumption of the proposed M3D logic are lower than those of previous versions. Despite the larger space and lower performance of the proposed M3D logic in comparison to the previous versions, it can be easily designed with a single modularized M3D-INV and without having to design all layouts of the logic gates separately.

• 전자공학회논문지 IE
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• v.48 no.2
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• pp.6-11
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• 2011

This paper describes the design of new method of propagation delay measurement in micro and nanostructures during characterization of ASIC standard library cell. Providing more accuracy timing information about library cell (NOR, AND, XOR, etc.) to the design team we can improve a quality of timing analysis inside of ASIC design flow process. Also, this information could be very useful for semiconductor foundry team to make correction in technology process. By comparison of the propagation delay in the CMOS element and result of analog SPICE simulation, we can make assumptions about accuracy and quality of the transistor's parameters. Physical implementation of phase error accumulation method(PHEAM) can be easy integrated at the same chip as close as possible to the device under test(DUT). It was implemented as digital IP core for semiconductor manufacturing process($0.11{\mu}m$, GL130SB). Specialized method helps to observe the propagation time delay in one element of the standard-cell library with up-to picoseconds accuracy and less. Thus, the special useful solutions for VLSI schematic-to-parameters extraction (STPE), basic cell layout verification, design simulation and verification are announced.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.285-288
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• 2000

In this paper, we propose a Reed-Solomon decoder for the DVD Reed-Solomon(RS) product code based on new efficient euclid cell architecture suitable for Modified Euclid Algorithm. We synthesized the RS decoder using Hyundai 0.65um CMOS standard cell library and compared the performance of the decoder with one of the conventional architectures. The result shows that the proposed euclid cell use about 32% less symbol time.

• The Journal of the Acoustical Society of Korea
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• v.15 no.5
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• pp.13-20
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• 1996

Recently, for implementation of neural networks extensive studies have been done especially VLSI technology has been regarded as the one of the most attractive means to implement neural networks. The main drawbacks of digital VLSI implementations are their large area and slow processing speed. In this paper to solve the speed and size problems we designed the efficient architecture using the binary convolution method for basic operation of neural cell, multiplication and addition. When it is used for implementing 3-layer network with 16 neural cell per layer that used neural cell based on binary convolution, clock of 50MHz and 26MCPS on 0.8${\mu}$ standard cell library has been achieved.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.38-43
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• 2006

In this paper, we propose the efficient dead pixel detection algorithm for CMOS image sensors and its hardware architecture. The CMOS image sensors as image input devices are becoming popular due to the demand for miniaturized, low-power and cost-effective imaging systems. However, the presence of the dead pixels degrade the image quality. To detect the dead pixels, the proposed algorithm is composed of scan, trace and detection step. The experimental results showed that it could detect 99.99% of dead pixels. It was designed in a hardware description language and total logic gate count is 3.2k using 0.25 CMOS standard cell library.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.10
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• pp.11-20
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• 2002

This paper proposes a hardware/software codesign of the MLSE equalizer for GSM.GPRS systems. We analyze algorithms of the MLSE equalizer which consists of a channel estimator using the correlation method and the Viterbi processor. We estimate the computational complexity requirement based on the simulation of TI TMS320C5x DSP. We also estimate the gate count from the results of logic synthesis using the samsung 0.5㎛ standard cell library (STD80). Based on the results of the complexity estimation and gate count, we propose the efficient software/hardware codesign of the MLSE equalizer based on the results of the complexity estimation and gate count.