• Title/Summary/Keyword: Standard Part Library

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A Study on A Proposal of Description for Archival Objects (행정박물 자료의 정리기술 표현에 관한 비교 분석)

  • Ra, Ill-Ok;Kim, Po-Ok
    • Journal of the Korean BIBLIA Society for library and Information Science
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    • v.17 no.2
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    • pp.137-155
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    • 2006
  • Objects which has been used for administration is a part of archives that holding merit of history, merit of evidence and merit of administration. But it does not be treated carefully as archival material also, it can not be found a study for the archival objects. Thus this study aims to suggest a description of the objects for management the objects appropriately. To derive a conclusion, this paper made a comparative by using the archival description of other nations such as General International Standard for Archival Description, Rules for Archival Description also refer to the cataloging rules which used for a long time to management materials at library such as Anglo-American Cataloging Rules, Korean Cataloging Rules. We divided the section into 7 area such as identity statement area, context area, content and structure area, condition of access and use area, allied material area, note area, and description control area for suggest a description for archival objects.

A Study on the Possibility of Initial Cost Saving in the New Housing Model Considering Long-life and Constructability - Focused on the Case Analysis with Converting Skeleton and Cladding to New Systems - (장수명화와 시공성을 고려한 새로운 공동주택 모델의 초기 비용절감 가능성 연구 - 구조체와 외장전환 사례분석을 중심으로 -)

  • Kim, Soo-Am;Shin, Sung-Eun;Chung, Joon-Soo;Shon, Young-Jin
    • Journal of the Korean housing association
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    • v.23 no.6
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    • pp.49-59
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    • 2012
  • This study suggested a new model in consideration of long life and constructability of apartment house suggested in the former part. New model suggested the possibility of cost saving based on the idea that people trend to reject because of the recognition that the new model would cost a lot of expense which work as the barrier for the expansion and distribution at the local market so as to prepare the ground for its activation. The Study was aimed at verifying the possibility of cost saving through comparing it with the existing standard apartment house system centered on the skeleton and cladding system among the new structural design models suggested in the former part. Assuming that these existing standard both models should be changed structural design into new model system, the quantity volume, cost and construction period along with the alteration of finished materials between two models were compared altogether. Simultaneously BIM library was built for easy taking-off bill of quantity and consideration of working methodology for construction working cycle, which was translated into construction cost so as to derive the cost of the two subject systems to be counted. Through the analysis, it was concluded that new model would secure variability in the future and constructability along with shortening the construction period (29%) and achieve cost saving (13%) of construction against the those of existing model.

Design of Sub-pixel Interpolation Circuit for Real-time Multi-decoder Supporting 4K-UHD Video Images (4K-UHD 영상을 지원하는 실시간 통합 복호기용 부화소 보간 회로 설계)

  • Lee, Sujung;Cho, Kyeongsoon
    • Journal of IKEEE
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    • v.19 no.1
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    • pp.1-9
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    • 2015
  • This paper proposes the design of sub-pixel interpolation circuit for real-time multi-decoder supporting 4K-UHD video images. The proposed sub-pixel interpolation circuit supports H.264, MPEG-4, VC-1 and new video compression standard HEVC. The common part of the interpolation algorithm used in each video compression standard is shared to reduce the circuit size. An intermediate buffer is effectively used to reduce the circuit size and optimize the performance. The proposed sub-pixel interpolation circuit was synthesised by using 130nm standard cell library. The synthesized gate-level circuit consists of 122,564 gates and processes 35~86 image frames per second for 4K-UHD video at the maximum operation frequency of 200MHz. Therefore, the proposed circuit can process 4K-UHD video in real time.

DESIGN OF E-BOOK VIEWER FOR PDA SUPPORTING ANNOTATION EDITING

  • Lee, Joo-Pyo;Hwang, Dae-Hoon
    • Journal of Korea Multimedia Society
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    • v.6 no.4
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    • pp.576-582
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    • 2003
  • Because of today's rapid growth of digital contents market and many benefits of electronic book, many people have considerable interest in E-book. Furthermore multifarious consortiums take an active part in standardization of I-book, and many E-book tools have been provided by software manufactures all over the world. E-book tools include editor for production of E-Book, viewer for reading, and the like. Especially in E-book viewer, annotation function has to be Included to put arrangement, summation, recording, comment, emphasis and after comprehension to practical use. In this paper, a E-book viewer with annotation is designed according to the specifications of EBKS, Korean standard. The proposed viewer is aimed to implement in PDA with embedded Linux, but developed in Windows 2000 platform. Because development environment and application environment are different each other, Qt-Library and cross-compiler are used for cross-platform development. The viewer support various functions such as adjusting of font size, hypertext linking, retrieval of specific word, and so forth. And in addition to these basic functions, annotation function is designed for the viewer, which can be used for re-usage and sharing of important information.

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Design and Implementation of a Java-Based Single Sign-On Library Supporting SAML (Security Assertion Markup Language) for Grid and Web Services Security (SAML을 이용한 그리드와 웹 서비스 보안을 위한 자바 기반 Single Sign-On 라이브러리의 설계 및 구현)

  • Jeong Jongil;Yu Seokhwan;Shin Dongkyoo;Shin Dongil;Cha Moohong
    • The KIPS Transactions:PartC
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    • v.12C no.3 s.99
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    • pp.339-346
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    • 2005
  • In recent years, the Grid development focus is transitioning from resources to services, A Grid Service is defined as a Web Service that provides a set of well-defined interfaces and follows specific conventions. SAML as a standard for Web Services which enables exchange of authentication, authorization, and profile information between different entities provides interoperability among different security services in distributed environments. In this paper, we implemented SAML API. By offering interoperability for non XML-based authentication technologies using SAML specification offering a method to integrate the existing Single Sign-On technologies, the API provides convenience for accessing different services in Grid architecture.

Utilization of machining templates to improve 5-axis CAM machining process (5축 CAM 가공 작업 프로세스 개선을 위한 가공 템플릿 활용)

  • Lee, Dong-Cheon;Kim, Seon-Yong
    • Design & Manufacturing
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    • v.11 no.1
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    • pp.45-49
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    • 2017
  • Currently, a lot of efforts to make increases the manufacturing efficiency have tried and there is growing the interest to implementing the machining operation through CAM automation and optimization. This kind of movement has shown gradually in 5X milling as well as 3X milling task. By the way, in case of 5X milling, it is difficult to hire the CAM experts who is an experience for 5X machining and also it has too big trouble to use them due to high cost. For this reason, you can see the manufacturer who is concern the CAM S/W to provide the NC automation program that beginners can generate easily the 5X milling in short term and the existing 5X milling process can be improved. These requirements need to make a NC automation process including the practical machining strategies same as the generation by NC expert. In order to support this, it is necessary to directly apply the 3D machining part based on NC template which includes the machining procedures, standard cutter library, auto machine area selection, analyze tool for part shape, machining condition setting considering the material stiffness to be provided by CimatronE and it should be created the 5axis machining data by a minimized operation. With user-friendly, CimatronE's NC machining automation tools improve the 5-axis machining process and speed up the process, maximizing work efficiency and improving product productivity compared to existing machining tasks.

Design of a Pipelined Binary Arithmetic Encoder for H.264/AVC (H.264/AVC를 위한 파이프라인 이진 산술 부호화기 설계)

  • Yun, Jae-Bok;Park, Tae-Geun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.6 s.360
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    • pp.42-49
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    • 2007
  • CABAC(Context-based Adaptive Binary Arithmetic Coding) among various entropy coding schemes which are used to improve compression efficiency in H.264/AVC has a high hardware complexity and the fast calculation is difficult because data dependancy exists in the bit-serial process. In this paper, the proposed architecture efficiently compose the renormalization process of binary arithmetic encoder which is an important part of CABAC used in H.264/AVC. At every clock cycle, the input symbol is encoded regardless of the iteration of the renormalization process for every input symbol. Also, the proposed architecture can deal with the bitsOutstanding up to 127 which is adopted to handle the carry generation problem and encode input symbol without stall. The proposed architecture with three-stage pipeline has been synthesized using the 0.18um Dongbu-Anam standard cell library and can be operated at 290MHz.

Design of Luma and Chroma Sub-pixel Interpolator for H.264 Motion Estimation (H.264 움직임 예측을 위한 Luma와 Chroma 부화소 보간기 설계)

  • Lee, Seon-Young;Cho, Kyeong-Soon
    • The KIPS Transactions:PartA
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    • v.18A no.6
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    • pp.249-254
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    • 2011
  • This paper describes an efficient design of the interpolation circuit to generate the luma and chroma sub-pixels for H.264 motion estimation. The circuit based on the proposed architecture does not require any input data buffering and processes the horizontal, vertical and diagonal sub-pixel interpolations in parallel. The performance of the circuit is further improved by simultaneously processing the 1/2-pixel and 1/4-pixel interpolations for luma components and the 1/8-pixel interpolations for chroma components. In order to reduce the circuit size, we store the intermediate data required to process all the interpolations in parallel in the internal SRAM's instead of registers. We described the proposed circuit at register transfer level and verified its operation on FPGA board. We also synthesized the gate-level circuit using 130nm CMOS standard cell library. It consists of 20,674 gates and has the maximum operating frequency of 244MHz. The total number of SPSRAM bits used in our circuit is 3,232. The size of our circuit (including logic gates and SRAM's) is smaller than others and the performance is still comparable to them.

Efficient VLSI Architecture for Factorization in Soft-Decision Reed-Solomon List Decoding (연판정 Reed-Solomon 리스트 디코딩의 Factorization을 위한 효율적인 VLSI 구조)

  • Lee, Sung-Man;Park, Tae-Guen
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.11
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    • pp.54-64
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    • 2010
  • Reed-Solomon (RS) codes are the most widely used error correcting codes in digital communications and data storage. Recently, Sudan found algorithm of list decoder for RS codes. List decoder has larger decoding radius than conventional hard-decision decoding algorithms and return more than one candidate polynomial. But, the algorithm includes interpolation and factorization step that demand massive computations. In this paper, an efficient architecture and processing schedule are proposed. The architecture consists of R-MAC, memories, and control unit. The R-MAC computes both of RC and PU steps that are main part of the factorization algorithm. The proposed architecture can achieve higher hardware utilization efficiency (HUE) and throughput by using efficient processing schedule and memory architecture. Also, the architecture can be designed flexibly with scalability for various applications. We design and synthesize our architecture using Dongbu-Anam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 330MHz.

Calculation of Low-Energy Reactor Neutrino Spectra for Reactor Neutrino Experiments

  • Riyana, Eka Sapta;Suda, Shoya;Ishibashi, Kenji;Matsuura, Hideaki;Katakura, Jun-ichi
    • Journal of Radiation Protection and Research
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    • v.41 no.2
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    • pp.155-159
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    • 2016
  • Background: Nuclear reactors produce a great number of antielectron neutrinos mainly from beta-decay chains of fission products. Such neutrinos have energies mostly in MeV range. We are interested in neutrinos in a region of keV, since they may take part in special weak interactions. We calculate reactor antineutrino spectra especially in the low energy region. In this work we present neutrino spectrum from a typical pressurized water reactor (PWR) reactor core. Materials and Methods: To calculate neutrino spectra, we need information about all generated nuclides that emit neutrinos. They are mainly fission fragments, reaction products and trans-uranium nuclides that undergo negative beta decay. Information in relation to trans-uranium nuclide compositions and its evolution in time (burn-up process) were provided by a reactor code MVP-BURN. We used typical PWR parameter input for MVP-BURN code and assumed the reactor to be operated continuously for 1 year (12 months) in a steady thermal power (3.4 GWth). The PWR has three fuel compositions of 2.0, 3.5 and 4.1 wt% $^{235}U$ contents. For preliminary calculation we adopted a standard burn-up chain model provided by MVP-BURN. The chain model treated 21 heavy nuclides and 50 fission products. The MVB-BURN code utilized JENDL 3.3 as nuclear data library. Results and Discussion: We confirm that the antielectron neutrino flux in the low energy region increases with burn-up of nuclear fuel. The antielectron-neutrino spectrum in low energy region is influenced by beta emitter nuclides with low Q value in beta decay (e.g. $^{241}Pu$) which is influenced by burp-up level: Low energy antielectron-neutrino spectra or emission rates increase when beta emitters with low Q value in beta decay accumulate Conclusion: Our result shows the flux of low energy reactor neutrinos increases with burn-up of nuclear fuel.