• 한국통신학회논문지
• /
• 제34권7A호
• /
• pp.568-573
• /
• 2009

본 논문에서 0.13um CMOS 공정으로 설계된 배터리 기반 휴대용 통신 시스템 구동용의 온칩 시동회로를 갖는 스텝다운 CMOS DC-DC 변환기를 제안하였다. 1MHz의 스위칭 주파수를 기반으로 설계된 벅 변환기에는 온칩 시동회로와 커패시터 멀티플라이어 기법을 이용한 보상회로를 포함시켰다. 칩 측정 결과 2.5V ${\sim}$3.3V의 입력 전압을 1.2V로 강압시키는데 최대 87.2%의 효율을 갖는다. 최대 부하 전류, 출력 전류 리플 및 전압 리플은 각각 500mA, 25mA, 24mV 이다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2007년도 추계학술대회 논문집 전력기술부문
• /
• pp.18-20
• /
• 2007

A coupling capacitor voltage transformer (CCVT) is used in an extra high voltage power system to obtain the standard low voltage signal for protection and measurement. To suppress the effects of ferro-resonance more effectively, a three winding CCVT is used. This paper proposes an algorithm for compensating the secondary voltage of the three winding CCVT. With the secondary voltage of the three winding CCVT, the secondary and tertiary currents are obtained; the primary winding current is obtained by considering non-linear characteristics of the core; the voltage across the capacitor and the inductor are calculated and then added to the measured voltage to compensate the secondary voltage. Test results indicate that the algorithm can reduce the errors of the three winding CCVT significantly.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2008년도 하계종합학술대회
• /
• pp.537-538
• /
• 2008

A step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in 0.18um CMOS standard process. In an effort to improve low load efficiency, this paper proposes the PFM (Pulse Frequency modulation) voltage mode 1MHz switching frequency step-down DC-DC converter with on-chip compensation. Capacitor multiplier method can minimize error amplifier compensation block size by 20%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87% for the output voltage of 1.8V (input voltage : 3.3V), maximum load current 500mA, and 0.14% output ripple voltage. The total core chip area is $mm^2$.

• Journal of Power Electronics
• /
• 제13권3호
• /
• pp.362-368
• /
• 2013

Commercial home appliances using remotely controlled systems consume electric power while in standby mode to prepare for receiving a remote turn-on signal. The proposed power system can significantly reduce standby power consumption without increasing cost. Furthermore, since a Electronic Double Layer Capacitor (EDLC) is used as an auxiliary power storage element, the life cycle is longer and system reliability can be better than with existing approaches. When the energy of the EDLC is not sufficient for turning on the appliance, the power system charges the EDLC without affecting the main system. The proposed power system is verified with a commercial LCD TV and a 3.93mW standby consumption is obtained. This standby consumption can be regarded as zero standby equipment according to the IEC-62031 standard.

• 전기학회논문지
• /
• 제57권6호
• /
• pp.938-943
• /
• 2008

Coupling capacitor voltage transformers(CCVTs) have been used in extra or ultra high voltage systems to obtain the standard low voltage signal for protection and measurement. For fast suppression of the phenomenon of ferroresonance, three winding CCVTs are used instead of two winding CCVTs. A tuning reactor is connected between a capacitor voltage divider and a voltage transformer to reduce the phase angle difference between the primary and secondary voltages in the steady state. Slight distortion of the secondary voltage is generated when no fault occurs. However, when a fault occurs, the secondary voltage of the CCVT has significant errors due to the transient components such as dc offset component and/or high frequency components resulting from the fault. This paper proposes an algorithm for compensating the secondary voltage of a three winding CCVT in the time domain. With the values of the measured secondary voltage of the three winding CCVT, the secondary, tertiary and primary currents and voltages are estimated; then the voltages across the capacitor and the tuning reactor are calculated and then added to the measured voltage. Test results indicate that the algorithm can successfully compensate the distorted secondary voltage of the three winding CCVT irrespective of the fault distance, the fault impedance and the fault inception angle as well as in the steady state.

• 전기학회논문지
• /
• 제57권6호
• /
• pp.909-914
• /
• 2008

A coupling capacitor voltage transformer(CCVT) is used in an extra or ultra high voltage system to obtain the standard low voltage signal for protection. To avoid the phase angle error between the primary and secondary voltages, a tuning reactor is connected between a capacitor and a voltage transformer. The inductance of the reactor is designed based on the power system frequency. If a fault occurs on the power system, the secondary voltage of the CCVT contains some errors due to a dc offset component and harmonic components resulting from the fault. The errors become severe in the case of a close-in fault. This paper proposes an algorithm for compensating the secondary voltage of a CCVT in the time-domain. From the measured secondary voltage of the CCVT, the secondary and primary currents are obtained; then the voltage across the capacitor and the inductor is calculated and then added to the measured secondary voltage to obtain the correct primary voltage. Test results indicate that the proposed algorithm can compensate the distorted secondary voltage of the CCVT irrespective of the fault distance, the fault inception angle, and the burden of the CCVT.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2006년도 제37회 하계학술대회 논문집 A
• /
• pp.266-267
• /
• 2006

A coupling capacitor voltage transformer (CCVT) is used in extra high voltage and ultra high voltage transmission systems to obtain the standard low voltage signal for protection and measurement. To obtain the high accuracy at the power system frequency, a tuning reactor is connected between a capacitor and a voltage transformer (VT). Thus, no distortion of the secondary voltage is generated when no fault occurs. However, when a fault occurs, the secondary voltage of the CCVT has some errors due to the transient components resulting from the fault. This paper proposes an algorithm for compensating the secondary voltage of the CCVT in the time domain. With the values of the secondary voltage of the CCVT, the secondary and the primary currents are obtained; then the voltage across the capacitor and the tuning reactoris calculated and then added to the measured secondary voltage. The proposed algorithm includes the effect of the non-linear characteristic of the VT and the influence of the ferro-resonance suppression circuit. Test results indicate that the algorithm can successfully compensate the distorted secondary voltage of the CCVT irrespective of the fault distance, the fault inception angle and the fault impedance.

• Transactions on Electrical and Electronic Materials
• /
• 제12권1호
• /
• pp.35-39
• /
• 2011

An electrically erasable programmable read-only memory (EEPROM) containing a stacked metal-insulator-metal (MIM) and n-well capacitor is proposed. It was fabricated using a 0.18 $\mu$m standard complementary metal-oxide semiconductor process. The depletion capacitance of the n-well region was effectively applied without sacrificing the cell-area and control gate coupling ratio. The device performed very similarly to the MIM capacitor cell regardless of the smaller cell area. This is attributed to the high control gate coupling ratio and capacitance. The erase speed of the proposed EEPROM was faster than that of the cell containing the MIM control gate.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2008년도 제39회 하계학술대회
• /
• pp.2030-2031
• /
• 2008

We have developed the calibration technique of the VT comparator using nonreactive standard resistors and a standard capacitor, which evaluates both accuracy and linearity of the VT comparator by comparing experimental values with theoretical values. The specification for phase displacement of VT comparator have been revaluated.

• 센서학회지
• /
• 제24권2호
• /
• pp.131-136
• /
• 2015

This paper presents a wide dynamic range complementary metal oxide semiconductor (CMOS) image sensor with column capacitor and feedback structure. The designed circuit has been fabricated by using $0.18{\mu}m$ 1-poly 6-metal standard CMOS technology. This sensor has dual mode operation using combination of active pixel sensor (APS) and passive pixel sensor (PPS) structure. The proposed pixel operates in the APS mode for high-sensitivity in normal light intensity, while it operates in the PPS mode for low-sensitivity in high light intensity. The proposed PPS structure is consisted of a conventional PPS with column capacitor and feedback structure. The capacitance of column capacitor is changed by controlling the reference voltage using feedback structure. By using the proposed structure, it is possible to store more electric charge, which results in a wider dynamic range. The simulation and measurement results demonstrate wide dynamic range feature of the proposed PPS.