• Journal of Korean Society for Quality Management
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• v.42 no.3
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• pp.279-290
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• 2014

Purpose: The purpose of this study is to propose adoption of QFD and Stage-gate in order to analyze the quality of korea defense system. Methods: Drawing change data of initial production phase in korea defense system were anlayzed and a practical method was proposed. Results: The results of this study are as follows; Off line Quality Control should be introduced in development phase. Specially, in case of defense system, the best method is QFD(Quality Function Deployment) and Stage-gate process. At first, QFD 1 step defines product planning from VOC(Voice Of Customer), QFD 2 step specifies part planning from product planning, QFD 3 step defines process planning from part planning, QFD 4 step defines production planning from previous process planning. Secondly, Stage-gate process is adopted. This study is proposed 5 stage-gate in case of korea defense development. Gate 1 is located after SFR(System Function Review), Gate 2 is located after PDR(Preliminary Design Review), Gate 3 is located after CDR(Critical Design Review), Gate 4 is located after TRR(Test Readiness Review) and Gate 5 is located before specification documentation submission. Conclusion: Off line QC(Quality Control) in development phase is necessary prior to on line QC(Quality Control) in p roduction phase. For the purpose of off line quality control, QFD(Quality Function Deployment) and Stage-gate process can be adopted.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.43 no.2
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• pp.65-71
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• 2020

Worldwide plant market keeps maintaining steady growth rate and along with this trend, domestic plant market and its contractors also maintain such growing tendency. However, in spite of its external growth, win-win growth of domestic material industry that occupies the biggest share in plant industry cost portion is extremely marginal in reality. Domestic plant material suppliers are required to increase awareness of domestic material brand by securing quality and reliability of international standard through improvement of design quality superior to that of overseas material suppliers. Improvement of design quality of plant material becomes an essential element, not an option, for survival of domestic plant industry and its suppliers. Under this background, in this study, priority and importance by each evaluation index was analyzed by materializing plant design stage through survey of experts and defining evaluation index by each design stage and based on this analysis result, evaluation index of stage-gate based decision-making process that may improve design quality of plant material was suggested. It is considered that by utilizing evaluation index of stage-gate based decision-making process being suggested in this study, effective and efficient decision-making of project decision-makers would be enabled and it would be contributory to improve design quality of plant material.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.5
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• pp.572-579
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• 1988

In this paper, a system of automatic placement and routing for gate array layout design is proposed. In the placement stage, the circuit is partitioned and using the concept of min-cut slicing, and each partitioned module is placed, so that the routing density over the entire chip be uniformized and the total wiring length be minimized. In the global routing stage, the concept of the probabilistic routing density is introduced to unify the wiring congestions in each channel. In the detailed routing stage, the multi-terminal nets are partitioned into the two-terminal nets. The ordered channel graph is proposed which implies the vertical and the horizontal constranint graphs simultaneously. And using the ordered channel graph, the proposed routing algorithm assigns the signal nets to the tracks. Also the proposed placement and routing algorithms are implimented on IBM/PC-AT to construct PC-level gate array layout system.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.2 no.2
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• pp.33-37
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• 2001

The synthesis of gates of injection-molded parts has been done empirically, since it requires profound knowledge about the gate design,. which is not available to designers through current CAD systems. GATEWAY is a knowledge module which contains knowledge to Permit non-experts as well as mold design experts to generate acceptable gate design of injection-molded parts. A knowledge-based CAD system is constructed by adding the knowledge module, GATEWAY, for gate synthesis and appropriate CAE programs for mold design analysis to an existing geometric modeler to provide designers, at the initial stage, with comprehensive process knowledge for gate synthesis. Performance analysis and feature-based geometric modeling.

• Transactions of the Korean Society of Automotive Engineers
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• v.2 no.6
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• pp.110-116
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• 1994

In this research, the tensile strength of molded parts and pressure distribution were analyzed to study the cavity filling stage and packing stage in injection molding. The measurement of cavity pressure was obtained by a data acquisition system with the installation of transducers in the cavity. Molded parts were tested by a universal testing machine to obtain the tensile strength. For the experimental work, the tensile strength of molded parts increased with longer packing time and exact freezing time of the gate was obtained by a cavity pressure curve. In addition, the effect of packing did not occur and tensile strength was almost constant after early 1.5 sec of the freezing time of gate. Density tended to be higher about 0.2% due to a larger degree of mold temperature and melt temperature. Also, changing pressure in the cavity was effectively sensed. Thereafter, the possibility of the development of pattern recognition expert system was confirmed on the basis of the experimental results.

• Journal of Korean Institute of Industrial Engineers
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• v.29 no.2
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.3
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• pp.189-196
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• 1989

In this paper, BICMOS gate array technology that has CMOS devices for logic applications and bipolar devices for driver applications is presented. An optimized poly gate p-well CMOS process is chosen to fabricate the BICMOS gate array system and the basic concepts to design these devices are to improve the characteristics of bipolar & CMOS device with simple process technology. As the results hFE value is 120(Ic=1mA) for transistor, and there is no short channel effects for CMOS devices which have Leff to 1.25um and 1.35um for n-channel, respectively, 0.8nx gate delay time of 41 stage ring oscillators is obtained.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.28 no.3B
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• pp.297-306
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• 2008

In order to determine the effects of lock gate expansion at the Lake Youngsan and Yeongam as well as increase in the width of the connecting channel of the two lakes on flood control downstream of the Youngsan River, an unsteady hydraulic flood routing was conducted by combining the Lake Youngsan and Yeongam as a single connected system. The coupled operation of the two lakes was found to have little effect when the widths of the lock gates and the connecting channel are set at the current level. It was also found that increasing the width of the connecting channel as well as the lock gate of the Lake Yeongam is an effective means of reducing the stage of the Lake Youngsan, whereas an increase in the width of the Lake Youngsan's lock gate had a relatively smaller effect. The extended width of the connecting channel leads to a rise in the stage of the Lake Yeongam. In order to reduce the elevated stage, The Lake Yeongam's lock gate must be expanded along with the Lake Yeongsan's lock gate. The analysis found that the stage of the Lake Yeongsan can be effectively controlled through adjustment of opening and shutting criteria of the connecting channel's lock gate, when diversion discharge between the lakes is increased as a result of expanding the width of the connecting channel.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04a
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• pp.187-190
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• 2000

We fabricated general photo diode, surface etched photo diode and floating gate MOSFET by CMOS process. In a design stage, we expect that surface etched photo diode will be improved as to photo sensitivity. However, because the surface of silicon was damaged in etching process, the surface etched diode had a high dark current as well as low photo current level. Finally, we examined the current-voltage properties for the floating gate MOSFET on n-well and confirmed that the device can be act as an efficient photo-sensor. The floating gate MOSFET was operated in parasitic bipolar transistor mode.

• Journal of Korean Society for Quality Management
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• v.48 no.3
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• pp.521-534
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• 2020

Purpose: This paper is to study the methodology of the development stage of the submarine vessel through the QMST/QCG system. Methods: In order to study the methodology for supporting the development stage of the submarine vessel system, the mission and role for QMST were defined, and the timing and detailed plans of the QCG review were established. Results: Through the analysis of the development stage of the ship's weapon system, QMST was formed, and roles were divided for each subdivision, and methods to effectively support the DAPA IPT were specified. In addition, QCG review timing and plans for submarine safety control lists were established. Conclusion: It is expected that the methodology in the development stage discussed in this study will be useful as a reference when supporting the general weapon system development stage in addition to similar equipment.