• 품질경영학회지
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• 제42권3호
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• pp.279-290
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• 2014

Purpose: The purpose of this study is to propose adoption of QFD and Stage-gate in order to analyze the quality of korea defense system. Methods: Drawing change data of initial production phase in korea defense system were anlayzed and a practical method was proposed. Results: The results of this study are as follows; Off line Quality Control should be introduced in development phase. Specially, in case of defense system, the best method is QFD(Quality Function Deployment) and Stage-gate process. At first, QFD 1 step defines product planning from VOC(Voice Of Customer), QFD 2 step specifies part planning from product planning, QFD 3 step defines process planning from part planning, QFD 4 step defines production planning from previous process planning. Secondly, Stage-gate process is adopted. This study is proposed 5 stage-gate in case of korea defense development. Gate 1 is located after SFR(System Function Review), Gate 2 is located after PDR(Preliminary Design Review), Gate 3 is located after CDR(Critical Design Review), Gate 4 is located after TRR(Test Readiness Review) and Gate 5 is located before specification documentation submission. Conclusion: Off line QC(Quality Control) in development phase is necessary prior to on line QC(Quality Control) in p roduction phase. For the purpose of off line quality control, QFD(Quality Function Deployment) and Stage-gate process can be adopted.

• 산업경영시스템학회지
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• 제43권2호
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• pp.65-71
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• 2020

Worldwide plant market keeps maintaining steady growth rate and along with this trend, domestic plant market and its contractors also maintain such growing tendency. However, in spite of its external growth, win-win growth of domestic material industry that occupies the biggest share in plant industry cost portion is extremely marginal in reality. Domestic plant material suppliers are required to increase awareness of domestic material brand by securing quality and reliability of international standard through improvement of design quality superior to that of overseas material suppliers. Improvement of design quality of plant material becomes an essential element, not an option, for survival of domestic plant industry and its suppliers. Under this background, in this study, priority and importance by each evaluation index was analyzed by materializing plant design stage through survey of experts and defining evaluation index by each design stage and based on this analysis result, evaluation index of stage-gate based decision-making process that may improve design quality of plant material was suggested. It is considered that by utilizing evaluation index of stage-gate based decision-making process being suggested in this study, effective and efficient decision-making of project decision-makers would be enabled and it would be contributory to improve design quality of plant material.

• 대한전자공학회논문지
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• 제25권5호
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• pp.572-579
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• 1988

In this paper, a system of automatic placement and routing for gate array layout design is proposed. In the placement stage, the circuit is partitioned and using the concept of min-cut slicing, and each partitioned module is placed, so that the routing density over the entire chip be uniformized and the total wiring length be minimized. In the global routing stage, the concept of the probabilistic routing density is introduced to unify the wiring congestions in each channel. In the detailed routing stage, the multi-terminal nets are partitioned into the two-terminal nets. The ordered channel graph is proposed which implies the vertical and the horizontal constranint graphs simultaneously. And using the ordered channel graph, the proposed routing algorithm assigns the signal nets to the tracks. Also the proposed placement and routing algorithms are implimented on IBM/PC-AT to construct PC-level gate array layout system.

• 한국산학기술학회논문지
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• 제2권2호
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• pp.33-37
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• 2001

본 논문은 사출성형제품의 게이트 설계를 합리적으로 수행하기 위해 사출금형설계전문가의 축적된 지식과 경험을 발췌·정리하여 지식베이스를 작성하였으며, 설계에 필요한 제품의 형상정보를 제공하기 위해 총칭형상과 특징형상 개념을 이용하여 특징형상을 정의하였다. 또한 지식베이스를 통해 산출된 설계결과를 기하학적 모델러와의 인터페이스를 통해 3차원 형상으로 보여지도록 하였으며 최종 생성된 3차원 기하학적 형상정보는 CAE 모듈이나 CAPP 모듈에서의 후속작업을 위해 제공될 수 있도록 구축되었다.

• 한국자동차공학회논문집
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• 제2권6호
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• pp.110-116
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• 1994

In this research, the tensile strength of molded parts and pressure distribution were analyzed to study the cavity filling stage and packing stage in injection molding. The measurement of cavity pressure was obtained by a data acquisition system with the installation of transducers in the cavity. Molded parts were tested by a universal testing machine to obtain the tensile strength. For the experimental work, the tensile strength of molded parts increased with longer packing time and exact freezing time of the gate was obtained by a cavity pressure curve. In addition, the effect of packing did not occur and tensile strength was almost constant after early 1.5 sec of the freezing time of gate. Density tended to be higher about 0.2% due to a larger degree of mold temperature and melt temperature. Also, changing pressure in the cavity was effectively sensed. Thereafter, the possibility of the development of pattern recognition expert system was confirmed on the basis of the experimental results.

• 대한산업공학회지
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• 제29권2호
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

• 한국통신학회논문지
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• 제14권3호
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• pp.189-196
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• 1989

본 논문에서는 BICMOS 게이트 어레이 시스템 구성시 내부의 논리회로 부분은 CMOS 소자로 입출력부는 바이폴라 소자를 이용할 수 있는 공정과 소자 개발을 하고자 하였다. BICMOS게이트 어레이 공정은 폴리게이트 p-well CMOS 공정을 기본으로 하였고, 소자설계의 기본개념은 공정흐름을 복잡하지 않게 하면서 바이폴라, CMOS 소자 각각의 특성을 좋게 하는데 두었다. 시험결과로서, npn1 트랜지스터의 hFE 특성은 120(Ic=1mA) 정도이고, CMOS 소자에서는 n-채널과 p-채널이 각각 1.25um, 1.35um 까지는 short channel effect 현상이 나타나지 않았고, 41stage ring oscillator의 게이트당 delay 시간은 0.8ns이었다.

• 대한토목학회논문집
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• 제28권3B호
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• pp.297-306
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• 2008

영산호의 배수갑문 확장, 영암호의 배수갑문, 연락수로의 확폭이 영산강 하류부 홍수위 조절에 미치는 영향을 분석하기 위하여, 영산호와 영암호를 하나의 연계시스템으로 구성하여 부정류 해석을 수행하였다. 영산호 배수갑문의 폭, 영암호 배수갑문의 폭, 연락수로의 폭이 현상태인 조건에서, 영산호-영암호 연계운영의 효과는 미미한 것으로 분석되었다. 영산호의 내수위를 낮추기 위해서는 연락수로의 폭과 영암호 배수갑문의 폭을 확장하는 것이 효과적이며, 영산호 배수갑문의 폭을 확장하는 것은 상대적으로 그 영향이 작은 것으로 분석되었다. 연락수로의 폭을 확장하는 것은 영암호의 내수위 상승을 유발하는데, 상승한 영암호의 내수위를 낮추기 위해서는 영암호 배수갑문과 영산호 배수갑문을 함께 확장하는 것이 필요하다. 연락수로의 폭을 확장함으로써 호소간 분기유량을 증대시키면, 연락수로 제수문의 개폐기준 조정을 통해 영산호의 내수위를 효과적으로 조절할 수 있는 것으로 분석되었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 디스플레이 광소자 분야
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• pp.187-190
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• 2000

We fabricated general photo diode, surface etched photo diode and floating gate MOSFET by CMOS process. In a design stage, we expect that surface etched photo diode will be improved as to photo sensitivity. However, because the surface of silicon was damaged in etching process, the surface etched diode had a high dark current as well as low photo current level. Finally, we examined the current-voltage properties for the floating gate MOSFET on n-well and confirmed that the device can be act as an efficient photo-sensor. The floating gate MOSFET was operated in parasitic bipolar transistor mode.

• 품질경영학회지
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• 제48권3호
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• pp.521-534
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• 2020

Purpose: This paper is to study the methodology of the development stage of the submarine vessel through the QMST/QCG system. Methods: In order to study the methodology for supporting the development stage of the submarine vessel system, the mission and role for QMST were defined, and the timing and detailed plans of the QCG review were established. Results: Through the analysis of the development stage of the ship's weapon system, QMST was formed, and roles were divided for each subdivision, and methods to effectively support the DAPA IPT were specified. In addition, QCG review timing and plans for submarine safety control lists were established. Conclusion: It is expected that the methodology in the development stage discussed in this study will be useful as a reference when supporting the general weapon system development stage in addition to similar equipment.