• Transactions of the Korean hydrogen and new energy society
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• v.23 no.4
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• pp.300-309
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• 2012

Long endurance is a key issue in the application of unmanned aerial vehicles. This study presents feasibility test results when fuel cell system as an alternative to the conventional engine is applied for the power of the UAV after the 150W fuel cell system is developed and packaged to the 1/4 scale super cub airplane. Fuel cell system is operated by dead-end method in the anode part and periodically purged to remove the water droplet in flow field during the operation. Oxygen in the air is supplied to the stack by the two air blowers. And fuel cell stack is water cooled by cooling circuit to dissipate the heat generated during the fuel cell operation. Weight balance is considered to integrate the stack and balance of plant (BOP) in package layout. In flight performance test, we demonstrated 4 times standalone take-off and landing. In the laboratory test simulating the flight condition to quantify the energy flow, the system is analyzed in detail. Sankey diagram shows that electric efficiency of the fuel cell system is 39.2%, heat loss 50.1%, parasitic loss 8.96%, and unreacted purged gas 1.67%, respectively compared to the total hydrogen input energy. Feasibility test results show that fuel cell system is high efficient and appropriate for the power of UAV.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.7-15
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• 2012

Semiconductor packages are increasingly moving toward miniaturization, lighter and multi-functions for mobile application, which requires highly integrated multi-stack package. To meet the industrial demand, the package and silicon chip become thinner, and ultra-thin packages will show serious reliability problems such as warpage, crack and other failures. These problems are mainly caused by the mismatch of various package materials and geometric dimensions. In this study we perform the numerical analysis of the warpage deformation and thermal stress of 4-layer stacked FBGA package after EMC molding and reflow process, respectively. After EMC molding and reflow process, the package exhibits the different warpage characteristics due to the temperature-dependent material properties. Key material properties which affect the warpage of package are investigated such as the elastic moduli and CTEs of EMC and PCB. It is found that CTE of EMC material is the dominant factor which controls the warpage. The results of RSM optimization of the material properties demonstrate that warpage can be reduced by $28{\mu}m$. As the silicon die becomes thinner, the maximum stress of each die is increased. In particular, the stress of the top die is substantially increased at the outer edge of the die. This stress concentration will lead to the failure of the package. Therefore, proper selection of package material and structural design are essential for the ultra-thin die packages.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2005.09a
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• pp.67-88
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• 2005

Mold-Flow 3 Die Stack CSP of Mold array packaging with different Gate types. As high density package option such as 3 or 4 die stacking technologies are developed, the major concerning points of mold related qualities such as incomplete mold, exposed wires and wire sweeping issues are increased because of its narrow space between die top and mold surface and higher wiring density. Full 3D rheokinetic simulation of Mold flow for 3 die stacking structure case was done with the rheological parameters acquired from Slit-Die rheometer and DSC of commercial EMC. The center gate showed severe void but corner gate showed relatively better void performance. But in case of wire sweeping related, the center gate type showed less wire sweeping than corner gate types. From the simulation results, corner gate types showed increased velocity, shear stress and mold pressure near the gate and final filling zone. The experimental Case study and the Mold flow simulation showed good agreement on the mold void and wire sweeping related prediction. Full 3D simulation methodologies with proper rheokinetic material characterization by thermal and rheological instruments enable the prediction of micro-scale mold filling behavior in the multi die stacking and other complicated packaging structures for the future application.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.57-63
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• 2006

For chip-stack package applications, Cu filling characteristics into trench vias of $75{\sim}10\;{\mu}m$ width and 3 mm length were investigated with variations of electroplating current density and current mode. At $1.25mA/cm^{2}$ of DC mode, Cu filling ratio higher than 95% was obtained for trench vias of $75{\sim}35{\mu}m$ width. When electroplated at DC $2.5mA/cm^{2}$, Cu filling ratios became inferior to those processed at DC $1.25mA/cm^{2}$. Pulse current mode exhibited Cu filling characteristics superior to DC current mode.

• Journal of Welding and Joining
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• v.31 no.6
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• pp.77-83
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• 2013

3D packaging technology using TSV (Through Silicon Via)has been studied in the recent years to achieve higher performance, lower power consumption and smaller package size because electrical line is shorter electrical resistivity than any other packaging technology. To stack TSV chips vertically, reliable and robust bonding technology is required because mechanical stress and thermal stress cause fracture during the bonding process. Cu pillar/solder ${\mu}$-bump bonding process is usually to interconnect TSV chips vertically although it has weak shape to mechanical stress and thermal stress. In this study, we suggest Insert-Bump (ISB) bonding process newly to stack TSV chips. Through experiments, we tried to find optimal bonding conditions such as bonding temperature and bonding pressure. After ISB bonding, we observed microstructure of bump joint by SEM and then evaluated properties of bump joint by die shear test.

• Journal of the Korean Society for Precision Engineering
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• v.31 no.10
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• pp.857-863
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• 2014

In this work, we introduce various bonding technologies for 3D package and suggest Insert-Bump bonding (ISB) process newly to stack multi-layer chips successively. Microstructure of Insert-Bump bonding (ISB) specimens is investigated with respect to bonding parameters. Through experiments, we study on find optimal bonding conditions such as bonding temperature and bonding pressure and also evaluate in the case of fluxing and no-fluxing condition. Although no-fluxing bonding process is applied to ISB bonding process, good bonding interface at $270^{\circ}C$ is formed due to the effect of oxide layer breakage.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.51-57
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• 2013

The current expanding mobile markets incessantly demands small form factor, low power consumption and high aggregate throughput for silicon-level integration such as memory to logic system. One of emerging solution for meeting this high market demand is 3D through silicon stacking (TSS) technology. Main challenges to bring 3D TSS technology to the volume production level are establishing a cost effective supply chain and building a reliable manufacturing processes. In addition, this technology inherently help increase number of IOs and shorten interconnect length. With those benefits, however, potential signal and power integrity risks are also elevated; increase in PDN inductance, channel loss on substrate, crosstalk and parasitic capacitance. This paper will report recent progress of wide IO memory to high count TSV logic device assembly development work. 28 nm node TSV test vehicles were fabricated by the foundry and assembled. Successful integration of memory wide IO chip with less than a millimeter package thickness form factor was achieved. For this successful integration, we discussed potential signal and power integrity challenges. This report demonstrated functional wide IO memory to 28 nm logic device assembly using 3D package architecture with such a thin form factor.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.1
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• pp.19-24
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• 2000

To make stacked chip packages far high-density packaging of memory chips used in workstations or PC severs, several lead-frames are to be connected vertically. Fer this purpose. Sn or Sn/Ag were electrochemically deposited on Cu lead-frames and their microstructures were examined by XRD and SEM. Then, two specimens were annealed at $250^{\circ}C$ for 10 min. and pressed to be joined. The shear stresses of joined lead-frames were measured fur comparison. In the case of Sn only, $Cu_3Sn$ was formed by the reaction of Sn and Cu lead-frames. In the case of Sn/Ag, besides $Cu_3Sn$. $Ag_3Sn$ was formed by the reaction of Sn and Ag. Compared to joined specimens made from Sn only, those made from Sn/Ag showed 1.2 times higher shear stress. This was attributed to the $Ag_3Sn$ phase formed at the joined interface.

• Journal of information and communication convergence engineering
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• v.12 no.1
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• pp.46-52
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• 2014

This article presents key research needs in three-dimensional integrated circuit (3D IC) architectural floorplanning. Architectural floorplaning is done at a very early stage of 3D IC design process, where the goal is to quickly evaluate architectural designs described in register-transfer level (RTL) in terms of power, performance, and reliability. This evaluation is then fed back to architects for further improvement and/or modifications needed to meet the target constraints. We discuss the details of the following research needs in this article: block-level modeling, through-silicon-via (TSV) insertion and management, and chip/package co-evaluation. The goal of block-level modeling is to obtain physical, power, performance, and reliability information of architectural blocks. We then assemble the blocks into multiple tiers while connecting them using TSVs that are placed in between hard IPs and inside soft IPs. Once a full-stack 3D floorplanning is obtained, we evaluate it so that the feedback is provided back to architects.

• Journal of Applied Reliability
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• v.16 no.4
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• pp.347-355
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• 2016

Purpose: With the advance of miniaturization of electronic products, stacked packages of high density semiconductors are commonly used. Potential failure modes and mechanisms of stacked packages are identified. Methods: Failure modes and mechanisms of thin chip stacked packages are determined through the categorization and failure analysis: delamination, non-wet, crack, ESD, EMI and the process related damages. Results: Those failure modes are not easy to find and require excessive amount time and effort for analysis and subsequent improvement. Conclusion: In this study, a method of estimating the failure rate based on the strength measurement is suggested.