• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.97.2-97
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• 1998

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2007.04a
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• pp.37-47
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• 2007

Factor : Structure Metal pad & SMO size Board level TC test : - Large SMO size better Board level Drop test : - Large SMO size better Factor : Structure Substrate thickness Board level TC test : - Thick substrate better Board level Drop test : - Substrate thickness is not a significant factor for drop test Factor : Material Solder alloy Board level TC test : - Not so big differences over Pb-free solder and NiAu, OSP finish Board level Drop test : - Ni/Au+SAC105, CuOSP+LF35 are better Factor : Material Pad finish Board level TC test : - NiAu/NiAu is best Board livel Drop test : - CuOSP is best Factor : Material Underfill Board level TC test - Several underfills (reworkable) are passed TCG x500 cycles Board level Drop test : - Underfill lots have better performance than non-underfill lots Factor : Process Multiple reflow Board level TC test : - Multiple reflow is not a significant actor for TC test Board level Drop test : N/A Factor : Process Peak temp Board level TC test : - Higher peak temperature is worse than STD Board level Drop test : N/A Factor : Process Stack method Board level TC test : - No big difference between pre-stack and SMT stack Board level Drop test : - Flux dipping is better than paste dipping but failure rate is more faster

• Journal of the Microelectronics and Packaging Society
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• v.14 no.3
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• pp.65-71
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• 2007

For chip-stack package applications, Cu filling characteristics into trench vias of $75{\sim}10\;{\mu}m$ width and 3 mm length were investigated with variations of the electroplating current density and the speed of a rotating disc electrode (RDE). Cu filling characteristics into trench vias were improved with increasing the RDE speed. There was a Nernst relationship between half width of trench vias of Cu filling ratio higher than 95% and the minimum RDE speed, and the half width of trenches with 95% Cu filling ratio was linearly proportional to the reciprocal of root of the minimum RED speed.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.16 no.3
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• pp.216-223
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• 2016

This paper proposes a new controller design method for a fork-type lifter (FTL) of a transportation mobile robot. The transportation robot needs to pick up a package from a stack on a storage shelf and move on by a planned path in a logistics center environment. The position of the storage shelf is recognized by reading a QR code on the floor, and using this position, the robot can move to reach the storage shelf and pick up the package. PID controllers and an adaptive controller are designed to control the velocity of two wheels and the position of the FTL. An adaptive controller for the lifter is designed to elevate up and down on a slideway to the correct height position of the package on the stack of the storage shelf. The simulation results show that the PID controllers can respond smoothly to the desired angular velocity and the adaptive controller can adapt quickly and correctly to the desired height.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2005.09a
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• pp.111-129
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• 2005

Pop provides OEMs and EMS with a platform to cost effectively expand options for logic + memory 3D integration - Expands device options by simplifying business logistics of stacking - Integration controlled at the system level to best match stacked combinations with system requirements - Eliminates margin stacking and expands technology reuse - Helps manage the huge cost impacts associated with increasing demand for multi media processing and memory. PoP is well timed to enable and leverage: - Mass customization of systems for different use (form, fit and function) requirements o Bband and apps processor + memory stack platforms - Logic transition to flip chip enables PoP size reduction o Area and height reduction. Industry standardization is progressing. Amkor provides full turn-key support for base package, memory package and full system integration.

• Journal of the Semiconductor & Display Technology
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• v.6 no.1 s.18
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• pp.17-22
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• 2007

Recent new packages such as MCP(Multi-Chip Package), QDP(Quadratic Die Package) and DDP(Dual Die Package) have stack type configuration. This kind of multi-layer package is thicker than single layer package. So there is need for the low height looping technology in wirebonder to make these packages thinner. There is stiff zone above ball in wirebonder wire which is called HAZ(Heat Affect Zone). When making low height loop (below $80\;{\mu}m$) with traditional forward loop, stiff wire in HAZ(Heat Affected Zone) above ball is bended and weakened. So the traditional forward looping method cannot be applied to low height loop. SSB(stand-off stitch) wire bonding method was applied to many packages which require very low loops. The drawback of SSB method is making frequent errors at making ball, neck damage above ball on lead and the weakness of ball bonding on lead. The alternative looping method is BNL(ball neckless) looping technology which is already applied to some package(DDP, QDP). The advantage of this method is faster in bonding process and making little errors in wire bonding compared with SSB method. This paper presents the result of BNL looping technology applied in assembly house and several issues related to low loop height consistence and BNL zone weakness.

• 한국신재생에너지학회:학술대회논문집
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• 2005.11a
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• pp.541-544
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• 2005

This study presents the integrated modeling approach to simulate the proton exchange membrane (PEM) fuel cell system for vehicle application. The fuel cell system consisting of stack and balance of plant (BOP) was simulated with MATLAB/Simulink environment to estimate the maximum system power and investigate the effect of BOP component sizing on system performance and efficiency. The PEM fuel cell stack model was established by using a semi-empirical modeling. To maximize the net efficiency of fuel cel1 system, multi-variable optimization code was adopted. Using this method the optimized operating values were obtained according to various system net power levels. The fuel cell model established was co-linked to AVL CRUISE, a vehicle simulation package. Through the vehicle simulation software, the fuel economy of fuel cell powered electric vehicle for two types of driving cycles was presented and compared. It is expected that this study tan be effectively employed in the basic BOP component sizing and in establishing system operation map with respect to net power level of fuel cell system.

• New & Renewable Energy
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• v.1 no.4 s.4
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• pp.43-48
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• 2005

This study presents the integrated modeling approach to simulate the proton exchange membrane [PEM] fuel cell system for vehicle application. The fuel cell system consisting of stack and balance of plant (BOP) was simulated with MATLAB/Simulink environment to estimate the maximum system power and investigate the effect of BOP component sizing on system performance and efficiency. The PEM fuel cell stack model was established by using a semi-empirical modeling. To maximize the net efficiency of fuel cell system, multi-variable optimization code was adopted. Using this method, the optimized operating values were obtained according to various system net power levels. The fuel cell model established was co-linked to AVL CRUISE, a vehicle simulation package. Through the vehicle simulation software, the fuel economy of fuel cell powered electric vehicle for two types of driving cycles was presented and compared. It is expected that this study can be effectively employed in the basic BOP component sizing and in establishing system operation map with respect to net power level of fuel cell system.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.111-119
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• 2005

Stack specimen with three dimensional interconnection structure through Cu via of $75{\mu}m$ diameter, $90{\mu}m$ height and $150{\mu}m$ pitch was successfully fabricated using subsequent processes of via hole formation with Deep RIE (reactive ion etching), Cu via filling with pulse-reverse electroplating, Si thinning with CMP, photolithography, metal film sputtering, Cu/Sn bump formation, and flip chip bonding. Contact resistance of Cu/Sn bump and Cu via resistance could be determined ken the slope of the daisy chain resistance vs the number of bump joints of the flip chip specimen containing Cu via. When flip- chip bonded at $270^{\circ}C$ for 2 minutes, the contact resistance of the Cu/Sn bump joints of $100{\times}100{\mu}m$ size was 6.7m$\Omega$ and the Cu via resistance of $75{\mu}m$ diameter, $90{\mu}m$ height was 2.3m$\Omega$.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.3-17
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• 2003

.Package Trend -> Memory : Lighter, Thinner, Smaller & High Density => SiP, 3D Stack -> MPU : High Pin Counts & Multi-functional => FCBGA .Interposer Trend -> Via - Unfilled Via => Filled Via - Staggered Via => Stacked Via -> Emergence of All-layer Build-up Processes -> Interposer Material Requirement => Low CTE, Low $D_{k}$, Low $D_{f}$, Halogen-free .New Technology Concept -> Embedded Passives, Imprint, MLTS, BBUL etc.