• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.4
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• pp.805-817
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• 1999

In this paper, the needs for introduction and adoption of MㆍHF DSC/NBDP system and for developments of its circuits and call sequences for use in the maritime mobile services for small-ships, leisure-ships and fishing ships are analyzed, discussed. Also design and implement for MㆍHF(1.6-4MHz) DSC/NBDP system is discussed. Most of casualties have been arisen from small-ships and fishing ships during last 5 years. So, the SAR schematic plans should been prepared to prevent casualties and facilitate the activities of SAR for those ships. DSC/NBDP for MㆍHF system is able to fulfill the roles of efficient SAR communication functions, and to advance the SAR system to small ships and fishing ships. This study is focused on the techniques of processing the DSC call sequences and the ARQ sequences of NBDP system. Especially ARQ sequences are expanded into processing of Korean letters, designed the call sequences and code conversion algorithm for Korean-code. It will be evaluated the availability of Korean-NBDP system. In designing the Transmitting circuits and Receiving circuits, for the carrier generation, DDS(Direct Digital Synthesizer) is used in stead of the Phase Locked Loop and frequency conversion by the mixer, BPF. And PSK modulation signals are directly generated by the controls of DDS, which show the characteristics of Spurious Free Dynamic Range are below -62dBc. Also, the monolithic U subsystem IC which provides various functional components, AD608 is used for designing the receiving circuitsㆍAnd the algorithm of Phasing methode for FSK demodulation are devised to process IF frequency 455kHz in the IF circuits.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.4
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• pp.819-830
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• 1999

NAVTEX system is an international automated direct-printing service, broadcast on 5181kHz and 490kHz, for the promulgation of navigational and meteorological warnings and urgent information to ships. With our government's adoption of the international convention for SAR(Search and Rescue) in 1993, various trials for the installation of NAVTEX system have been executed by the government committee, relating laboratory and experts. An important consideration of the installation for NAVTEX system is the availability that could broadcast messages written in korean letter. Also, the receiver which can process the signal demodulated from the two frequencies, 518kHz and 490kHz, should be developed and supplied in domestic. In this paper, the code table and algorithm for conversions between NAVTEX characters and Korean Letters are studied, and signal processing techniques of code conversion are developed. Circuit design and implementation of the NAVTEX simulator using the Direct Digital Synthesizer are discussed, code conversion algorithm and signal processing technique of the NAVTEX transmission are programmed in its circuits. For evaluating the its functional characteristics, receiving module which has I-Q channel structure is designed. From the measurements of simulator, the characteristics show the frequency stability of the $(\pm)2Hz$ and Spurious free dynamic range is -63dBc. And the simulator can generate simultaneously wanted signal and several interfere signals. So, its capability is valuable for designers of the transmitting system and NAVTEX receiver, for provider as testing facilities of the type approval.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.6
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• pp.87-96
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• 1999

For analog optical transmission of narrow-band microwave signal, a novel all-optical linearization technique of electro-absorption (EA) optical modulator by using dual modulation scheme is proposed and theoretically investigated. By using the dual modulation scheme where the sub-modulator has a different length, DC bias and band-gap wavelength, the DC bias operation point where the third-order intermodulation products of ~30dB and the following increase of spurious free dynamic range (SFDR) of ~20dB wave achieved in sub-octave narrow band operation.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1444-1445
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• 2008

최근 Wireless Local Area Network(WLAN), Wide-band Code Division Multiple Access(WCDMA), CDMA2000, Bluetooth 등 다양한 모바일 통신 시스템에 대한 수요가 증가하고 있다. 이와 같은 모바일 통신 시스템에는 70dB이상의 SFDR(Spurious Free Dynamic Range)을 가진 ADC(Analog-to-Digital Converter)가 사용된다. 본 논문에서는 모바일 통신 시스템을 위한 SFDR 70dBc의 성능을 제공하는 10비트, 100Msps 파이프라인 ADC를 제안한다. 제안한 ADC는 요구되는 해상도 및 속도 사양을 만족시키기 위해 3단 파이프라인 구조를 채택하였으며, 입력단 SHA(Sample and Hold)회로에는 Nyquist 입력에서도 10비트 이상의 정확도로 신호를 샘플링하기 위해 부트스트래핑 기법 기반의 샘플링 스위치를 적용하였다. residue amplifier 회로에는 전력을 줄이기 위해 8배 residue amplifier 대신 3개의 2배 ressidue amplifier를 사용하였다. ADC의 높은 사양을 만족시키기 위해서는 높은 이득을 가지는 op-amp가 필수적이다. 제안한 ADC 는 0.18um CMOS 공정으로 설계되었으며, 100Msps의 동작 속도에서 70dBc 수준의 SFDR과 60dB 수준의 SNDR(Signal to Noise and Distortion Ratio)을 보여준다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.685-691
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• 2003

This work describes a 3 V 12b 100 MS/s CMOS digital-to-analog converter (DAC) for high-speed communication system applications. The proposed DAC is composed of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs, considering linearity, power consumption, chip area, and glitch energy. The low-glitch switch driving circuit is employed to improve the linearity and the dynamic performance. Current sources of the DAC are laid out separately from the current-cell switch matrix core. The prototype DAC is implemented in a 0.35 urn n-well single-poly quad-metal CMOS technology. The measured DNL and INL of the prototype DAC are within $\pm$0.75 LSB and $\pm$1.73 LSB, respectively, and the spurious-free dynamic range (SFDR) is 64 dB at 100 MS/s with a 10 MHz input sinewave. The DAC dissipates 91 mW at 3 V and occupies the active die area of 2.2 mm ${\times}$ 2.0 mm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.129-140
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• 2017

In this paper, a $4{\times}32$-channel neural recording system capable of acquiring neural signals is introduced. Four 32-channel neural recording ICs, complex programmable logic devices (CPLDs), a micro controller unit (MCU) with USB interface, and a PC are used. Each neural recording IC, implemented in $0.18{\mu}m$ CMOS technology, includes 32 channels of analog front-ends (AFEs), a 32-to-1 analog multiplexer, and an analog-to-digital converter (ADC). The mid-band gain of the AFE is adjustable in four steps, and have a tunable bandwidth. The AFE has a mid-band gain of 54.5 dB to 65.7 dB and a bandwidth of 35.3 Hz to 5.8 kHz. The high-pass cutoff frequency of the AFE varies from 18.6 Hz to 154.7 Hz. The input-referred noise (IRN) of the AFE is $10.2{\mu}V_{rms}$. A high-resolution, low-power ADC with a high conversion speed achieves a signal-to-noise and distortion ratio (SNDR) of 50.63 dB and a spurious-free dynamic range (SFDR) of 63.88 dB, at a sampling-rate of 2.5 MS/s. The effectiveness of our neural recording system is validated in in-vivo recording of the primary somatosensory cortex of a rat.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.8
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• pp.54-61
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• 1999

This paper proposes a new optic link structure applicable to broad-band wireless access microcellularsystem servicing in the millimeter wave frequency band. The proposed structure utilizes photonic mixing by exploiting the nonlinear property of EOMs, which leads to the frequency up-conversion at the CS and thus, electrical mixing at a BS is not required. Moreover, via transmitting an additional optical millimeter wave carrier into the Bs, the dispenses with an active optic source, which miniaturizes the BS. We analyze CNR, IM3/C in the downlink and SFDR in the uplink. Through simulation using the typical parameter values we also show the feasibility of the proposed system based on the requirements in the current microcellular system.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2022.06a
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• pp.339-343
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• 2022

In this study, a method for simplifying the structure of the VDES RF receiver, and the gain control method of the receiver to comply with the international standard in this structure was described. The input level of the wanted signal and unwanted signal to the receiver was defined, and when the two signals were input, the saturation state at the ADC was checked at the receiver output. As a result of the simulation by the circuit simulator, it was satisfied that the output power of the receiver was in the SFDR region of ADC with respect to the adjacent channel interference ratio, intermodulation, and blocking level. Through this study, it was found that the structure of th proposed RF receiver conforms to the international standard.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.47-54
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• 2006

This work proposes a dual-channel 6b 1GS/s ADC for ultra wide-band communication system applications. The proposed ADC based on a 6b interpolated flash architecture employs wide-band open-loop track-and-hold amplifiers, comparators with a wide-range differential difference pre-amplifier, latches with reduced kickback noise, on-chip CMOS references, and digital bubble-code correction circuits to optimize power, chip area, and accuracy at 1GS/s. The ADC implemented in a 0.18um 1P6M CMOS technology shows a signal-to-noise-and-distortion ratio of 30dB and a spurious-free dynamic range of 39dB at 1GS/s. The measured differential and integral non-linearities of the prototype ADC are within 1.0LSB and 1.3LSB, respectively. The dual-channel ADC has an active area of $4.0mm^2$ and consumes 594mW at 1GS/s and 1.8V.