• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.685-691
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• 2003

This work describes a 3 V 12b 100 MS/s CMOS digital-to-analog converter (DAC) for high-speed communication system applications. The proposed DAC is composed of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs, considering linearity, power consumption, chip area, and glitch energy. The low-glitch switch driving circuit is employed to improve the linearity and the dynamic performance. Current sources of the DAC are laid out separately from the current-cell switch matrix core. The prototype DAC is implemented in a 0.35 urn n-well single-poly quad-metal CMOS technology. The measured DNL and INL of the prototype DAC are within $\pm$0.75 LSB and $\pm$1.73 LSB, respectively, and the spurious-free dynamic range (SFDR) is 64 dB at 100 MS/s with a 10 MHz input sinewave. The DAC dissipates 91 mW at 3 V and occupies the active die area of 2.2 mm ${\times}$ 2.0 mm.

• Journal of Electrical Engineering and Technology
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• v.7 no.4
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• pp.570-575
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• 2012

In a wireless communication RF transmitter, the output of a quadrature modulator (QM) is distorted by not only the linear imperfection features such as in/quadrature-phase (I/Q) input gain imbalance, local phase imbalance, and local gain imbalance but also the nonlinear imperfection features such as direct current (DC) offset and mixer nonlinearity related to in-band spurious signal. In this paper, we propose the unified QM model to analyze the combined effects of the linear and nonlinear imperfection features on the performance of the QM. The unified QM model consists of two identical nonlinear systems and modified I/Q inputs based on the two-port nonlinear mixer model. The unified QM model shows that the output signals can be expressed by mixer circuit parameters such as intercept point and gain as well as the imperfection features. The proposed approach is validated by not only simulation but also measurement.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.57-65
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• 2002

In this paper, a 2.5V 10-bit 300MSPS CMOS D/A Converter is described. The architecture of the D/A Converter is based on a current steering 8+2 segmented type, which reduces non-linearity error and other secondary effects. In order to achieve a high performance D/A Converter, a novel current cell with a low spurious deglitchnig circuit and a novel inverse thermomeer decoder are proposed. To verify the performance, it is integrated with $0.25{\mu}m$ CMOS 1-poly 5-metal technology. The effective chip area is $1.56mm^2$ and power consumption is about 84mW at 2.5V power supply. The simulation and experimental results show that the glitch energy is 0.9pVsec at fs=100MHz, 15pVsec at fs=300MHz in worst case, respectively. Further, both of INL and DNL are within ${\pm}$1.5LSB, and the SFDR is about 45dB when sampling, frequency, is 300MHz and output frequency is 1MHz.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.5
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• pp.371-378
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• 2015

In this paper, a different type of pulse width modulation (PWM) control scheme for a buck converter is introduced. The proposed buck converter uses PWM with frequency hopping and a low quiescent.current low dropout (LDO) voltage regulator with a power supply rejection ratio enhancer to reduce high spurs, harmonics and output voltage ripples. The low quiescent.current LDO voltage regulator is not described in this paper. A three-bit binary-to-thermometer decoder scheme and voltage ripple controller (VRC) is implemented to achieve low voltage ripple less than 3mV to increase the efficiency of the buck converter. An internal clock that is synchronized to the internal switching frequency is used to set the hopping rate. A center frequency of 2.5MHz was chosen because of the bluetooth low energy (BLE) application. This proposed DC-DC buck converter is available for low-current noise-sensitive loads such as BLE and radio frequency loads in portable communications devices. Thus, a high-efficiency and low-voltage ripple is required. This results in a less than 2% drop in the regulator's efficiency, and a less than 3mV voltage ripple, with -26 dBm peak spur reduction operating in the buck converter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.83-94
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• 2003

In this paper. a highly linear and low glitch CMOS current mode digital-to-analog converter (DAC) by self calibration bias circuit is proposed. The architecture of the DAC is based on a current steering 6＋4 segmented type and new switching scheme for the current cell matrix, which reduced non-linearity error and graded error. In order to achieve a high performance DAC . novel current cell with a low spurious deglitching circuit and a new inverse thermometer decoder are proposed. The prototype DAC was implemented in a 0.35${\mu}{\textrm}{m}$ n-well CMOS technology. Experimental result show that SFDR is 60 ㏈ when sampling frequency is 32MHz and DAC output frequency is 7.92MHz. The DAC dissipates 46 mW at a 3.3 Volt single power supply and occupies a chip area of 1350${\mu}{\textrm}{m}$ ${\times}$750${\mu}{\textrm}{m}$.

• Journal of Environmental Science International
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• v.25 no.2
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• pp.267-280
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• 2016

Ground echo is radar return from stationary targets such as buildings and trees. Wind vectors from the wind profile radar in Gangneung are affected by ground echoes due to the complex mountainous terrain located to the west and the south. These ground echoes make a spurious peak close to the direct current (DC) line signal in Doppler spectra. Wind vectors polluted by ground clutters were determined from spectra of oblique beams. After eliminated the terrain echoes, the accuracy of wind vector compared with radiosonde was improved about 68.4% and its relative coefficient was increased from 0.58 to 0.97.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.5
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• pp.2249-2253
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• 2011

This paper analyzed the problems of the Korean output regulation in the relevant band through an analytic comparison of the current trend of each country and their standard values concerning the technical standard of low power u-IT equipments. In connection with the standard value of technical values of each country, which has been proposed in the registration of the appropriate electric wave, the paper aims to propose the standard value that could actually be introduced for suitable low power u-IT installations in Korea. Provided that the Korean standard may be upgraded based on the tolerances of technical standards proposed in this paper, this is expected to be committed to the distribution and advancement of low power u-IT equipments; and further, it is anticipated to be prepared with competitiveness not only in the Korean communications market, but also in the international communications market.

• The Bulletin of The Korean Astronomical Society
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• v.36 no.2
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• pp.82.1-82.1
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• 2011

Korea Astronomy and Space Science Institute (KASI) operates 2 solar radio observing facilities, e-CALLISTO (Earthwide network of Compound Astronomical Low-cost Low-frequency Instrument for Transportable Observatory) station and Korean Solar Radio Burst Locator (KSRBL). Although e-CALLISTO tracking system improvement.is underway, at least 6 new events were observed in this year. Software development for KSRBL is in progress. The antenna calibration software was updated and flux calibration software was developed. Also the automatic daily overview spectrum monitoring system is now operational. We found solutions to several problems including spurious data and FPGA board communication. However, a few minor unsolved hardware problems still persist. Meanwhile, at least 6 new events were observed by KSRBL in this year, and a comparative study with HXR is currently underway.

• The KSFM Journal of Fluid Machinery
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• v.13 no.4
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• pp.31-36
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• 2010

Free energy based lattice Boltzmann method (LBM) has been used to simulate the rising bubble flows with large density ratio. LBM with compact discretization is able to reduce the spurious current of the static bubble test and be satisfied with the Laplace law. The terminal rise velocity and shape of the bubbles are dependent on Eotvos number, Morton number and Reynolds number. For single bubble flows, simulations are executed for various Eotvos number, Morton number and Reynolds number, and the results are agreed well with the experiments. For multiple bubbles, the bubble flow characteristics are related by the vortex pattern of the leading bubble. The coalescence of the bubbles are simulated successfully and the subsequent results are presented. The present method is validated for static, dynamic bubble test cases and compared to the numerical, experimental results.

• ETRI Journal
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• v.42 no.4
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• pp.549-561
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• 2020

We developed a 0.1-㎛ metamorphic high electron mobility transistor and fabricated a W-band monolithic microwave integrated circuit chipset with our in-house technology to verify the performance and usability of the developed technology. The DC characteristics were a drain current density of 747 mA/mm and a maximum transconductance of 1.354 S/mm; the RF characteristics were a cutoff frequency of 210 GHz and a maximum oscillation frequency of 252 GHz. A frequency multiplier was developed to increase the frequency of the input signal. The fabricated multiplier showed high output values (more than 0 dBm) in the 94 GHz-108 GHz band and achieved excellent spurious suppression. A low-noise amplifier (LNA) with a four-stage single-ended architecture using a common-source stage was also developed. This LNA achieved a gain of 20 dB in a band between 83 GHz and 110 GHz and a noise figure lower than 3.8 dB with a frequency of 94 GHz. A W-band image-rejection mixer (IRM) with an external off-chip coupler was also designed. The IRM provided a conversion gain of 13 dB-17 dB for RF frequencies of 80 GHz-110 GHz and image-rejection ratios of 17 dB-19 dB for RF frequencies of 93 GHz-100 GHz.