• 제목/요약/키워드: Solution annealing

검색결과 500건 처리시간 0.043초

Improvement of Device Characteristic on Solution-Processed InGaZnO Thin-Film-Transistor (TFTs) using Microwave Irradiation

  • Moon, Sung-Wan;Cho, Won-Ju
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제15권2호
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    • pp.249-254
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    • 2015
  • Solution-derived amorphous indium-gallium-zinc oxide (a-IGZO) thin-film-transistor (TFTs) were developed using a microwave irradiation treatment at low process temperature below $300^{\circ}C$. Compared to conventional furnace-annealing, the a-IGZO TFTs annealed by microwave irradiation exhibited better electrical characteristics in terms of field effect mobility, SS, and on/off current ratio, although the annealing temperature of microwave irradiation is much lower than that of furnace annealing. The microwave irradiated TFTs showed a smaller $V_{th}$ shift under the positive gate bias stress (PGBS) and negative gate bias stress (NGBS) tests owing to a lower ratio of oxygen vacancies, surface absorbed oxygen molecules, and reduced interface trapping in a-IGZO. Therefore, microwave irradiation is very promising to low-temperature process.

Optimized Local Relocation for VLSI Circuit Modification Using Mean-Field Annealing

  • Karimi, Gholam Reza;Verki, Ahmad Azizi;Mirzakuchaki, Sattar
    • ETRI Journal
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    • 제32권6호
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    • pp.932-939
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    • 2010
  • In this paper, a fast migration method is proposed. Our method executes local relocation on a model placement where an additional module is added to it for modification with a minimum number of displacements. This method is based on mean-field annealing (MFA), which produces a solution as reliable as a previously used method called simulated annealing. The proposed method requires substantially less time and hardware, and it is less sensitive to the initial and final temperatures. In addition, the solution runtime is mostly independent of the size and complexity of the input model placement. Our proposed MFA algorithm is optimized by enabling module rotation inside an energy function called permissible distances preservation energy. This, in turn, allows more options in moving the engaged modules. Finally, a three-phase cooling process governs the convergence of problem variables called neurons or spins.

다수제품의 수익성 최대화를 위한 설비입지선정 문제 (The Maximal Profiting Location Problem with Multi-Product)

  • 이상헌;백두현
    • 한국경영과학회지
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    • 제31권4호
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    • pp.139-155
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    • 2006
  • The facility location problem of this paper is distinguished from the maximal covering location problem and the flxed-charge facility location problem. We propose the maximal profiting location problem (MPLP) that is the facility location problem maximizing profit with multi-product. We apply to the simulated annealing algorithm, the stochastic evolution algorithm and the accelerated simulated annealing algorithm to solve this problem. Through a scale-down and extension experiment, the MPLP was validated and all the three algorithm enable the near optimal solution to produce. As the computational complexity is increased, it is shown that the simulated annealing algorithm' is able to find the best solution than the other two algorithms in a relatively short computational time.

Simulated Annealing 알고리듬을 이용한 SAM-X 추가전력의 최적배치 (Efficient Simulated Annealing Algorithm for Optimal Allocation of Additive SAM-X Weapon System)

  • 이상헌;백장욱
    • 산업공학
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    • 제18권4호
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    • pp.370-381
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    • 2005
  • This study is concerned with seeking the optimal allocation(disposition) for maximizing utility of consolidating old fashioned and new air defense weapon system like SAM-X(Patriot missile) and developing efficient solution algorithm based on simulated annealing(SA) algorithm. The SED(selection by effectiveness degree) procedure is implemented with an enhanced SA algorithm in which neighboring solutions could be generated only within the optimal feasible region by using a specially designed PERTURB function. Computational results conducted on the problem sets with a variety of size and parameters shows the significant efficiency of our SED algorithm over existing methods in terms of both the computation time and the solution quality.

패킷 통신 네트워크 설계를 위한 시뮬레이티드 애닐링 방법에서 초기해와 후보해 생성방법 (Generating Mechanisms of Initial and Candidate Solutions in Simulated Annealing for Packet Communication Network Design Problems)

  • 임동순;우훈식
    • 한국경영과학회지
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    • 제29권3호
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    • pp.145-155
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    • 2004
  • The design of a communication network has long been a challenging optimization problem. Since the optimal design of a network topology is a well known as a NP-complete problem, many researches have been conducted to obtain near optimal solutions in polynomial time instead of exact optimal solutions. All of these researches suggested diverse heuristic algorithms that can be applied to network design problems. Among these algorithms, a simulated annealing algorithm has been proved to guarantee a good solution for many NP-complete problems. in applying the simulated annealing algorithms to network design problems, generating mechanisms for initial solutions and candidate solutions play an important role in terms of goodness of a solution and efficiency. This study aims at analyzing these mechanisms through experiments, and then suggesting reliable mechanisms.

Placement 확률 진화 알고리즘의 설계와 구현 (Design and Implementation of a Stochastic Evolution Algorithm for Placement)

  • 송호정;송기용
    • 융합신호처리학회논문지
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    • 제3권1호
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    • pp.87-92
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    • 2002
  • 배치(Placement)는 VLSI 회로의 physical design에서 중요한 단계로서 회로의 성능을 최대로 하기 위하여 회로 모듈의 집합을 배치시키는 문제이며, 배치 문제에서 최적의 해를 얻기 위해 클러스터 성장(cluster growth), 시뮬레이티드 어닐링(simulated annealing; SA), ILP(integer linear programming)등의 방식이 이용된다. 본 논문에서는 배치 문제에 대하여 확률 진화 알고리즘(stochastic evolution algorithm; StocE)을 이용한 해 공간 탐색(solution space search) 방식을 제안하였으며, 제안한 방식을 시뮬레이티드 어닐링 방식과 비교, 분석하였다.

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어댑티드 회로 배치 유전자 알고리즘의 설계와 구현 (Design and Implementation of a Adapted Genetic Algorithm for Circuit Placement)

  • 송호정;김현기
    • 디지털산업정보학회논문지
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    • 제17권2호
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    • pp.13-20
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    • 2021
  • Placement is a very important step in the VLSI physical design process. It is the problem of placing circuit modules to optimize the circuit performance and reliability of the circuit. It is used at the layout level to find strongly connected components that can be placed together in order to minimize the layout area and propagation delay. The most popular algorithms for circuit placement include the cluster growth, simulated annealing, integer linear programming and genetic algorithm. In this paper we propose a adapted genetic algorithm searching solution space for the placement problem, and then compare it with simulated annealing and genetic algorithm by analyzing the results of each implementation. As a result, it was found that the adaptive genetic algorithm approaches the optimal solution more effectively than the simulated annealing and genetic algorithm.

Characterization of Sol-Gel Derived Antimony-doped Tin Oxide Thin Films for Transparent Conductive Oxide Application

  • Woo, Dong-Chan;Koo, Chang-Young;Ma, Hong-Chan;Lee, Hee-Young
    • Transactions on Electrical and Electronic Materials
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    • 제13권5호
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    • pp.241-244
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    • 2012
  • Antimony doped tin oxide (ATO) thin films on glass substrate were prepared by the chemical solution deposition (CSD) method, using sol-gel solution synthesized by non-alkoxide precursors and the sol-gel route. The crystallinity and electrical properties of ATO thin films were investigated as a function of the annealing condition (both annealing environments and temperatures), and antimony (Sb) doping concentration. Electrical resistivity, carrier concentration, Hall mobility and optical transmittance of ATO thin films were improved by Sb doping up to 5~8 mol% and annealing in a low vacuum atmosphere, compared to the undoped tin oxide counterpart. 5 mol% Sb doped ATO film annealed at $550^{\circ}C$ in a low vacuum atmosphere showed the highest electrical properties, with electrical resistivity of about $8{\sim}10{\times}10^{-3}{\Omega}{\cdot}cm$, and optical transmittance of ~85% in the visible range. Our research demonstrates the feasibility of low-cost solution-processed transparent conductive oxide thin films, by controlling the appropriate doping concentration and annealing conditions.

용액 공정으로 형성된 n-ZTO/p-SiC 이종접합 열처리 효과 (Effects of Annealing on Solution Processed n-ZTO/p-SiC Heterojunction)

  • 정영석;구상모
    • 한국전기전자재료학회논문지
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    • 제28권8호
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    • pp.481-485
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    • 2015
  • We investigated the effects of annealing on the electrical and thermal properties of ZTO/4H-SiC heterojunction diodes. A ZTO thin film layer was grown on p-type 4H-SiC substrate by using solution process. The ZTO/SiC heterojunction structures annealed at $500^{\circ}C$ show that $I_{on}/I_{off}$ increases from ${\sim}5.13{\times}10^7$ to ${\sim}1.11{\times}10^9$ owing to the increased electron concentration of ZTO layer as confirmed by capacitance-voltage characteristics. In addition, the electrical characterization of ZTO/SiC heterojunction has been carried out in the temperature range of 300~500 K. When the measurement temperature increased from 300 K to 500 K, the reverse current variation of annealed device is higher than as-grown device, which is related to barrier height in the ZTO/SiC interface. It is shown that annealing process is possible to control the electrical characteristics of ZTO/SiC heterojunction diode.

Polytetrafluoroethylene 분말 현탁액을 통한 다공성 박막 제조 및 에너지 발생소자 응용 (Fabrication of Porous Polytetrafluoroethylene thin Film from Powder Dispersion-solution for Energy Nanogenerator Applications)

  • 박일규
    • 한국분말재료학회지
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    • 제24권2호
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    • pp.102-107
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    • 2017
  • Porous polytetrafluoroethylene (PTFE) thin films are fabricated by spin-coating using a dispersion solution containing PTFE powders, and their crystalline properties are investigated after thermal annealing at various temperatures ranging from 300 to $500^{\circ}C$. Before thermal annealing, the film is densely packed and consists of many granular particles 200-300 nm in diameter. However, after thermal annealing, the film contains many voids and fibrous grains on the surface. In addition, the film thickness decreases after thermal annealing owing to evaporation of the surfactant, binder, and solvent composing the PTFE dispersion solution. The film thickness is systematically controlled from 2 to $6.5{\mu}m$ by decreasing the spin speed from 1,500 to 500 rpm. A triboelectric nanogenerator is fabricated by spin-coating PTFE thin films onto polished Cu foils, where they act as an active layer to convert mechanical energy to electrical energy. A triboelectric nanogenerator consisting of a PTFE layer and Al metal foil pair shows typical output characteristics, exhibiting positive and negative peaks during applied strain and relief cycles due to charging and discharging of electrical charge carriers. Further, the voltage and current outputs increase with increasing strain cycle owing to accumulation of electrical charge carriers during charge-discharge.