• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.55-61
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• 2008

This paper shows quantitative reliability evaluations of a Bluetooth module through extending previous qualitative methods limited to structure reliability tests and solder joint reliability tests for Bluetooth modules. Accelerated Life Testing (ALT) of the modules using temperature difference in temperature cycling as an accelerated stress was conducted for quantitative reliability evaluation under field environment conditions. Lifetime distribution parameters were estimated using the failure times obtained through the ALT, and then Coffin-Manson model was implemented. Results of the ALT showed that the failure mode of the modules was open and the failure mechanisms are both crack and delamination. The ALT reproduced the failure mode and mechanisms of failed Bluetooth modules collected from the field. Further, a quantitative reliability evaluation method with respect to various temperature differences in temperature cycling was proposed in this paper. $B_{10}$ lifetime of the module for the temperature difference $70^{\circ}C$ using the proposed method would be estimated as about 4 years.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.768-771
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• 2003

The impulse between launch vehicle and atmosphere can generate a lot of noise and vibration during the process of launching a satellite. Structurally, electronic equipment (KOMPSAT 2, RDU : Remote Drive Unit) of a satellite consists of aluminum case containing PCB (Printed circuit boards). Each PCB has resistors and IC (Integrated circuits). Noise and vibration of wide frequency band are transferred to the inside of fairing, subsequently creating vibration of the electronic equipment of the satellite. In this situation. random vibration can cause malfunctioning of the electronic equipment of the device. Furthermore, when tile frequency of random vibration meets with natural frequency of PCB. fatigue fracture nay occur in the part of solder joint. The launching environment, thus. needs to be carefully considered when designing the electronic equipment of a satellite. In general. the safety of the electronic equipment is supposed to be related to the natural frequency, shapes of mode and dynamic deflection of PCB in the electronic equipment. Structural vibration analysis of PCB and its electronic components can be performed using either FEM(Finite Element Method) or vibration test. In this study. the natural frequency and dynamic deflection of PCB are measured by FEM, aud the safety of the electronic components of PCB is being evaluated according to the results. This study presents a unique method for finite element modeling and analysis of PCB and its electronic components. The results of FEA are verified by vibration test. The method proposed herein may be applicable to various designs from the electronic equipments of a satellite to home electronics.

• Proceedings of the KWS Conference
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• 2009.11a
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• pp.77-77
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• 2009

ELV(; End of Life Vehicles)를 비롯한 최근 환경 동향은 자동차 전장 모듈에 대하여 다양한 무연 솔더 적용을 요구하고 있다. 특히 자동차 엔진룸과 트랜스미션은 가동 중 고온 및 진동의 지속적인 영향을 받기 때문에 이와 유사한 환경에서의 신뢰성 연구가 필요한 시점이다. 이에 본 연구에서는 Sn3.5Ag, Sn0.7Cu, Sn5.0Sb 솔더 조성에 대하여 복합환경 조건하에서 접합부 신뢰성을 평가하였다. 복합환경을 구현하기 위하여 $-40{\sim}150^{\circ}C$ 범위의 온도 사이클과 랜덤 진동을 동시에 인가하였으며, 진동 가속도 3G, 진동주파수는 10~1000Hz 로 설정하여 자동차 환경을 충족하였다. 복합시험의 1 cycle 은 20 시간이며, 총 120 시간의 시험 동안 진동의 영향 및 진동과 고온이 동시에 작용하였을 경우의 영향에 대해 비교하였다. 테스트 모듈 제작을 위해 450 um 의 솔더볼이 적용되었으며, 각 조성의 솔더볼을 이용하여 BGA test chip 제작하였고, 제작된 BGA test chip 은 다시 daisy chain PCB 위에 실장 및 리플로우 공정을 통해 접합되었다. 테스트 동안 In-situ 로 저항의 변화를 관찰하여 파단의 유무를 판단하였고 전자주사현미경을 통해 파괴 기전을 평가하였다. 복합시험 시간에 따른 전단강도를 측정하였으며, 각 조성에 대하여 상이한 전단강도 변화를 관찰하였다. 계면 IMC 형상은 전단강도 변화에 영향을 주었으며, 특히 높은 온도가 IMC 성장을 촉진시켜 전단강도 감소에 영향을 주었다. 본 복합환경 시험 조건에서는 Sn0.7Cu 가 가장 안정적이었으며, 파단면을 관찰한 결과 연성파괴 모드가 관찰되었다.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.04a
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• pp.35-43
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• 2001

Flip chip assembly on organic substrates using ACAs have received much attentions due to many advantages such as easier processing, good electrical performance, lower cost, and low temperature processing compatible with organic substrates. ACAs are generally composed of epoxy polymer resin and small amount of conductive fillers (less than 10 wt.%). As a result, ACAs have almost the same CTE values as an epoxy material itself which are higher than conventional underfill materials which contains lots of fillers. Therefore, it is necessary to lower the CTE value of ACAs to obtain more reliable flip chip assembly on organic substrates using ACAs. To modify the ACA composite materials with some amount of conductive fillers, non-conductive fillers were incorporated into ACAs. In this paper, we investigated the effect of fillers on the thermo-mechanical properties of modified ACA composite materials and the reliability of flip chip assembly on organic substrates using modified ACA composite materials. Contact resistance changes were measured during reliability tests such as thermal cycling, high humidity and temperature, and high temperature at dry condition. It was observed that reliability results were significantly affected by CTEs of ACA materials especially at the thermal cycling test. Results showed that flip chip assembly using modified ACA composites with lower CTEs and higher modulus by loading non-conducting fillers exhibited better contact resistance behavior than conventional ACAs without non-conducting fillers. Microwave model and high-frequency measurement of the ACF flip-chip interconnection was investigated using a microwave network analysis. ACF flip chip interconnection has only below 0.1nH, and very stable up to 13 GHz. Over the 13 GHz, there was significant loss because of epoxy capacitance of ACF. However, the addition of $SiO_2filler$ to the ACF lowered the dielectric constant of the ACF materials resulting in an increase of resonance frequency up to 15 GHz. Our results indicate that the electrical performance of ACF combined with electroless Wi/Au bump interconnection is comparable to that of solder joint.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.4
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• pp.89-94
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• 2019

Glass base sealant is required as a ceramic-ceramic joining material between α-alumina insulation cap and β-alumina electrolyte tube in the development of NaS battery cell package for electrical energy storage system. The fabrication of glass frit by thermal quenching method, phase analysis, particle size analysis, coefficient of thermal expansion and surface roughness according to the glass compositions were analyzed for the fabrication of glass sealing paste for ceramic-ceramic joining. Also, a new evaluation method of the adhesion strength of glass sealant at the small area in ceramic-ceramic joining component was proposed using conventional Dage bond tester that was used to measure the adhesion of solder ball joint.

• Current Photovoltaic Research
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• v.8 no.4
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• pp.124-128
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• 2020

Output power of photovoltaic (PV) modules installed outdoors decreases every year due to environmental conditions such as temperature, humidity, and ultraviolet irradiations. In order to promote the installation of PV modules, the reliability must be guaranteed. One of the important factors affecting reliability is intermetallic compounds (IMC) layer formed in ribbon solder joint. For this reason, various studies on soldering properties between the ribbon and cell have been performed to solve the reliability deterioration caused by excessive growth of the IMC layer. However, the IMC layer of the PV module interconnected by multi-wires has been studied less than using the ribbon. It is necessary to study soldering characteristics of the multi-wire module for improvement of its reliability. In this study, we analyzed the growth of IMC layer of the PV module with multi-wire and the degradation of output power through damp-heat test. The fabricated modules were exposed to damp-heat conditions (85 ºC and 85 % relative humidity) for 1000 hours and the output powers of the modules before and after the damp-heat test were measured. Then, the process of dissolving ethylene vinyl acetate (EVA) as an encapsulant of the modules was performed to observe the IMC layer. The growth of IMC layer was evaluated using OM and FE-SEM for cross-sectional analysis and EDS for elemental mapping. Based on these results, we investigated the correlation between the IMC layer and output power of modules.

• Journal of Aerospace System Engineering
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• v.18 no.2
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• pp.12-20
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• 2024

The application of reinforcement design to ensure the structural safety of electronics in small satellites is limited by the spatial constraints of the satellite structure during launch vibrations. Additionally, a reliable evaluation approach is needed for mounting highly integrated devices that are susceptible to fatigue failure. Although the Steinberg fatigue failure theory has been used to assess the structural integrity of electronic devices, recent studies have highlighted its theoretical limitations. In this paper, we propose a structural methodology based on the critical strain theory to design the digital control unit (DCU) of the X-band SAR payload component for the small SAR technology experimental project (S-STEP), a small satellite constellation. To validate the design, we conducted modal and random analyses using simplified modeling techniques. Based on our methodology, we ultimately demonstrated the structural safety of the electronics through analysis results, safety margin derivation, and functional tests conducted both before and after the launch test.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.9-15
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• 2009

Compared to the flip-chip process using solder bumps, Cu pillar bump technology can accomplish much finer pitch without compromising stand-off height. Flip-chip process with Cu pillar bumps can also be utilized in radio-frequency packages where large gap between a chip and a substrate as well as fine pitch interconnection is required. In this study, Cu pillars with and without Sn caps were electrodeposited and flip-chip-bonded together to form the Cu-Sn-Cu sandwiched joints. Contact resistances and die shear forces of the Cu-Sn-Cu sandwiched joints were evaluated with variation of the height of the Sn cap electrodeposited on the Cu pillar bump. The Cu-Sn-Cu sandwiched joints, formed with Cu pillar bumps of $25-{\mu}m$ diameter and $20-{\mu}m$ height, exhibited the gap distance of $44{\mu}m$ between the chip and the substrate and the average contact resistance of $14\;m{\Omega}$/bump without depending on the Sn cap height between 10 to $25\;{\mu}m$.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.3
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• pp.55-62
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• 2001

With a spread of BGA, CSP and fine pitch devices, the need of flatter surface finish in bare board is becoming more critical in solderability. The electroless Ni/Au plating has a solution of these needs and also has being spread to apply to surface finish for bare board in many electronic goods. But, the electroless Ni/Au plating had several issues such as Ni oxidation and phosphorous contents. Before this study, we studied on the effect of BGA solderability in electroless Ni/Au plating and chose some major factors such as the oxidation property of NiP plating and warpage of board. Firstly, we made test board with various plating conditions and improved the plating property through the improvement of NiP oxidation reducing P content. Also, we minimized the warpage of board with the improvement of inner layer structure and the analysis of warpage. For the evaluation of solderability, we analyzed the warpage of board and the plating property after mounting BGA on the board with optimizing conditions. The solder joint of BGA is investigated by SEM(Scanning Electronic Microscope) and OM(Optical Microscope). The composition of joint is used by EDS(Energy Dispersive Spectroscopy). We analyzed the fracture strength and mode by ball shear teser.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.67-73
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• 2009

Compared to the chip-bonding process utilizing solder bumps, flip chip process using Cu pillar bumps can accomplish fine-pitch interconnection without compromising stand-off height. Cu pillar bump technology is one of the most promising chip-mounting process for RF packages where large gap between a chip and a substrate is required in order to suppress the parasitic capacitance. In this study, Cu pillar bumps and Sn bumps were electroplated on a chip and a substrate, respectively, and were flip-chip bonded together. Contact resistance and chip shear force of the Cu pillar bump joints were measured with variation of the electroplated Sn-bump height. With increasing the Sn-bump height from 5 ${\mu}m$ to 30 ${\mu}m$, the contact resistance was improved from 31.7 $m{\Omega}$ to 13.8 $m{\Omega}$ and the chip shear force increased from 3.8 N to 6.8 N. On the contrary, the aspect ratio of the Cu pillar bump joint decreased from 1.3 to 0.9. Based on the variation behaviors of the contact resistance, the chip shear force, and the aspect ratio, the optimum height of the electroplated Sn bump could be thought as 20 ${\mu}m$.