• Proceedings of the Korea Information Processing Society Conference
• /
• 2011.11a
• /
• pp.223-226
• /
• 2011

반도체 공정에서 부품의 결함을 찾는 것은 완제품의 품질 개선을 위해 중요하다. 현재까지 많은 비전 알고리즘들이 부품의 결함을 찾기 위해 적용되고 있다. 그러나 이런 알고리즘 대부분은 2D 방식의 검사 방식에 머물고 있다. 그러나 이런 2D방식의 검사 방법은 반도체 칩의 Lead나 Pad 그리고 Solder Joint와 같이 3D 정보에 의해 불량 유무를 판결해야 하는 곳에 적용하기 어렵다. 이에 본 논문에서는 PMP(Phase Measuring Profilometry)방법에 의해 반도체 칩의 Lead부분을 검사하기 위한 시스템 구성과 방법을 제안한다.

• Journal of the Microelectronics and Packaging Society
• /
• v.20 no.4
• /
• pp.53-58
• /
• 2013

An innovative packaging solution, Flip Chip with Copper (Cu) Column bond on lead (BOL) Enhanced Process (fcCuBE$^{(R)}$) delivers a cost effective, high performance packaging solution over typical bond on capture pad (BOC) technology. These advantages include improved routing efficiency on the substrate top layer thus allowing conversion functionality; furthermore, package cost is lowered by means of reduced substrate layer count and removal of solder on pad (SOP). On the other hand, as electronic packaging technology develops to meet the miniaturization trend from consumer demand, reliability testing will become an important issue in advanced technology area. In particular, electromigration (EM) of flip chip bumps is an increasing reliability concern in the manufacturing of integrated circuit (IC) components and electronic systems. This paper presents the results on EM characteristics on BOL and BOC structures under electrical current stressing in order to investigate the comparison between two different typed structures. EM data was collected for over 7000 hours under accelerated conditions (temperatures: $125^{\circ}C$, $135^{\circ}C$, and $150^{\circ}C$ and stress current: 300 mA, 400 mA, and 500 mA). All samples have been tested without any failures, however, we attempted to find morphologies induced by EM effects through cross-sectional analysis and investigated the interfacial reaction characteristics between BOL and BOC structures under current stressing. EM damage was observed at the solder joint of BOC structure but the BOL structure did not show any damage from the effects of EM. The EM data indicates that the fcCuBE$^{(R)}$ BOL Cu column bump provides a significantly better EM reliability.

• Proceedings of the KWS Conference
• /
• 2009.11a
• /
• pp.80-80
• /
• 2009

패키징 구조의 발전이 점차 중요한 문제로 대두되어, 칩의 집적 기술의 발전에 따라 실장기술에서도 고속화, 소형화, 미세피치화, 고정밀화, 고밀도화가 요구되고있다. 최근 선진국을 중심으로 전자 전기기기 및 부품의 실장기술에서도 환경 친화적인 기술을 요구함에 따라, 저에너지 공정 및 무연 실장 기술에 대한 연구가 활발하게 진행되고 있다. 기존의 SOP(Small Out-line Package), QFP(Quad Flat Package) 등은 소형화, 다핀화, 고속화, 실장성에 한계가 있기 때문에, SMT(Surface Mount Technology) 형식으로 된 BGA(Ball Grid Array)가 휴대형 전화를 비롯한 기타 전자 부품 실장에 널리 사용되고 있다. BGA ball shear 법은 BGA 모듈의 생산 및 취급 중에 발생할지도 모르는 기판에 수평으로 작용하는 기계적인 전단력에 BGA solder ball이 견딜 수 있는 정도를 측정하기 위해 사용되는 시험법이다. 전단 시험에 의한 전단 강도의 측정 외에 전기전도도 측정, 파면 관찰, 이동거리(displacement), 유한요소 해석법 등을 병행하여 시험법의 신뢰성 향상에 대한 연구가 이루어지고 있다. 본 실험에서는 지름이 $500{\mu}m$인 Sn-3.5Ag 솔더볼을 이용하여 세라믹 기판을 접합하여 BGA 패키지를 완성하였다. 상부 기판에 솔더볼을 정렬시켜 리플로우 방법으로 접합 한 후 솔더볼이 접합된 상부 기판과 하부 기판을 접합 하여 시편을 제작하였다. 접합된 시편들은 $150^{\circ}C$에서 0~800시간 열처리를 실시하였고, 열처리를 하면서 각각 $3{\times}10^2A/cm^2,\;5{\times}10^3A/cm^2$의 전류를 인가하였다. 시편들을 전단 시험기를 이용하여 솔더볼의 기계적 특성 평가를 하였으며, 계면 반응을 관찰하였다.

• Korean Journal of Metals and Materials
• /
• v.49 no.8
• /
• pp.635-641
• /
• 2011

The effect of high shear speed on shear force, shear energy and fracture surface was investigated for the solder joint of a $Sn-_{3.0}Ag-_{0.5}Cu$ ball. For both ENIG and OSP pads, the shear force increased with an increase in shearing speed to 0.3 m/s. However, for an ENEPIG pad, the shear force increased with an increase in shear speed to 0.6 m/s and kept almost constant afterward. The shear energy decreased with an increase in shearing speed for ENIG and OSP pads. For the ENEPIG pad, however, the shear energy almost remained constant in a shearing speed range 0.3-3.0 m/s. The fracture mode analysis revealed that the amount of brittle fracture for the ENIG and the OSP pads increased with shearing speed, and a complete brittle fracture appeared at 1.0 m/s for ENIG and 2.0 m/s for OSP. However, the ENEPIG pad showed only a ductile fracture until 0.25 m/s, and a full brittle fracture didn't occur up to 3.0 m/s. The fracture mode matched well with the shear energy. The results from the high speed shear test of SAC305 were similar to those of SAC105.

• Journal of the Microelectronics and Packaging Society
• /
• v.31 no.1
• /
• pp.35-42
• /
• 2024

Recently, with the miniaturization and high integration of semiconductor chips, the bump bridge phenomenon caused by fine pitches is drawing attention as a problem. Accordingly, Cu pillar bump, which can minimize the bump bridge phenomenon, is widely applied in the semiconductor package industry for fine pitch applications. When exposed to a high-temperature environment, the thickness of the intermetallic compound (IMC) formed at the joint interface increases, and at the same time, Kirkendall void is formed and grown inside some IMC/Cu and IMC interfaces. Therefore, it is important to control the excessive growth of IMC and the formation and growth of Kirkendall voids because they weaken the mechanical reliability of the joints. Therefore, in this study, isothermal aging evaluation of Cu pillar bump joints with a CS (Cu+ Sn-1.8Ag Solder) structure was performed and the corresponding results was reported.

• Journal of the Microelectronics and Packaging Society
• /
• v.19 no.4
• /
• pp.57-64
• /
• 2012

Ball shear test was performed by test variables such as loading speed and annealing time in order to investigate the effect of surface finishes on the bonding strength of Sn-1.2Ag-0.7Cu-0.4In Pb-free solder. The shear strength increased and the ductility decreased with increasing shear speed. With increasing shear speed, the electroless nickel immersion gold (ENIG) finish showed dominant brittle fracture mode, while organic solderability preservative (OSP) finish showed pad open fracture mode. The shear strength and toughness for both surface finishes decreased with increasing annealing time under the high-speed shear test of 500 mm/s. Typically, the thickness of intermetallic compound increased with increasing annealing time, which means that exposure of brittle fracture became much easier. With increasing annealing time, the both ENIG and OSP finishes exhibited the pad open fracture mode. Overall, ENIG finish showed higher shear strength rather than OSP finish due to its superior barrier stability.

• Journal of the Microelectronics and Packaging Society
• /
• v.21 no.1
• /
• pp.1-6
• /
• 2014

Flip chip bonded LED packages possess lower thermal resistance than wire bonded LED packages because of short thermal path. In this study, thermal and bonding properties of flip chip bonded high brightness LED were evaluated for Au-Sn thermo-compression bonded LEDs and Sn-Ag-Cu reflow bonded LEDs. For the Au-Sn thermo-compression bonding, bonding pressure and bonding temperature were 50 N and 300oC, respectively. For the SAC solder reflow bonding, peak temperature was $255^{\circ}C$ for 30 sec. The shear strength of the Au-Sn thermo-compression joint was $3508.5gf/mm^2$ and that of the SAC reflow joint was 5798.5 gf/mm. After the shear test, the fracture occurred at the isolation layer in the LED chip for both Au-Sn and SAC joints. Thermal resistance of Au-Sn sample was lower than that of SAC bonded sample due to the void formation in the SAC solder.

• Journal of the Microelectronics and Packaging Society
• /
• v.6 no.3
• /
• pp.9-18
• /
• 1999

In this study, Metallugical properties between Sn-3.5Ag, Sn-37Pb eutectic solders and Au/Ni/cu substrate according to time span above the melting point were investigated. A conventional reflow soldering machine wert used for this study and time span above the melting point was determined by changing peak soldering temperature and conveyor speed. As results, scallop type intermetallic compounds of $Ni_3Sn_4$ were formed at joint interface and no Cu-Sn compounds were found at all; Ni layer performed as a barrier for Cu diffusion. As the peak soldering temperature increased, thickness of the intermetallic compound layer increased; maximum thickness of the scallop-layer was 2.2$\mu\textrm{m}$. The shape of scallops were transformed from hemi-sphere type to elliptical shape with smaller size. Micro-hardness of the solder joint decreased as the eutectic structure of Sn-3.5Ag and Sn-37Pb increased.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2004.09a
• /
• pp.93-99
• /
• 2004

At present, LG Electronics pushes ahead to eliminate the Pb(Lead) -a hazardous material- from all products. Especially, we have performed to select the optimum standard composition of lead free alloy for the application to products for about 3 years from 2000. These days, we have the chance for applying to the mass-production. This project constructed the system for applying the lead free solders on consumer electronic products, which is one of the major products of the LG Electronics. To select the lead free solders with corresponding to the product features, we have passed through the test and applied with Sn-3.0Ag-0.5Cu alloy system to our products, and for the application to the high melting temperature composition, we secured the thermal resistance of the many parts and substrate and optimized the processing conditions. We have operated the temperature cycling test and the high temperature storage test under the standards to confirm the reliability of the products. On these samples, we considered the consequence of our decision by the operating test. For the long life time of the product, we have operated the temperature cycling test at $-45^{\circ}C-+125^{\circ}C$, 1 cycle/hour, 1000 cycles. Also we have tested the tin whisker growth about lead free plating on lead finish. We have analyzed with the SEM, EDS and any other equipment for confirming the failure mode at the joint and the tin whisker growth on lead free finish.

• Journal of the Korean Society for Precision Engineering
• /
• v.21 no.8
• /
• pp.120-128
• /
• 2004

The impulse between launch vehicle and atmosphere can generate a lot of noise and vibration during the process of launching a satellite. Structurally, the electronic equipment of a satellite consists of an aluminum case containing PCB. Each PCB has resistors and IC. Noise and vibration of the wide frequency band are transferred to the inside of fairing, subsequently creating vibration of the electronic equipment of the satellite. In this situation, random vibration can cause malfunctioning of the electronic equipment of the device. Furthermore, when the frequency of random vibration meets with natural frequency of PCB, fatigue fracture may occur in the part of solder joint. The launching environment, thus, needs to be carefully considered when designing the electronic equipment of a satellite. In general, the safety of the electronic equipment is supposed to be related to the natural frequency, shapes of mode and dynamic deflection of PCB in the electronic equipment. Structural vibration analysis of PCB and its electronic components can be performed using either FEM or vibration test. In this study, the natural frequency and dynamic deflection of PCB are measured by FEM, and the safety of the electronic components of PCB is evaluated according to the results. This study presents a unique method for finite element modeling and analysis of PCB and its electronic components. The results of FEA are verified by vibration test. The method proposed herein may be applicable to various designs ranging from the electronic equipments of a satellite to home electronics.