• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.17-26
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• 2010

Pb-Sn solder is rapidly being replaced by lead-free solder for board-level interconnection in microelectronic package assemblies due to the environmental protection requirement. There is a general lack of mechanical reliability information available on the lead-free solder. In this study, thermo-mechanical behaviors of wire-bond plastic ball grid array (WB-PBGA) package assemblies are characterized by high-sensitivity moire interferometry. Experiments are conducted for two types of WB-PBGA packages that have Pb-Sn solder and lead-free solder as joint interconnections. Using real-time moire setup, fringe patterns are recorded and analyzed for several temperatures. Bending deformations of the assemblies and average strains of the solder balls are investigated and compared for the two type of WB-PBGA package assemblies. Results show that shear strain in #3 solder ball located near the chip shadow boundary is dominant for the failure of the package with Pb-Sn solder, while normal strain in #7 most outer solder ball is dominant for that with lead-free solder. It is also shown that the package with lead-free solder has much larger bending deformation and 10% larger maximum effective strain than the package with Pb-Sn solder at same temperature level.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.21-26
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• 2002

Solder flip chip bumping and subsequent coining processes on PCB were investigated to solve the warpage problem of organic substrates for high pin count flip chip assembly by providing good co-planarity. Coining of solder bumps on PCB has been successfully demonstrated using a modified tension/compression tester with height, coining rate and coining temperature variables. It was observed that applied loads as a function of coined height showed three stages as coining deformation : (1) elastic deformation at early stage, (2) linear increase of applied load, and (3) rapid increase of applied load. In order to reduce applied loads for coining solder bumps on PCB, effects of coining process parameters were investigated. Coining loads for solder bump deformation strongly depended on coining rates and coining temperatures. As coining rates decreased and process temperature increased, coining loads decreased. Among the effect of two factors on coining loads, it was found that process temperature had more significant effect to reduce applied coining loads during the coining process. Lower coining loads were needed to prevent substrate damages such as micro-via failure and build-up dielectric layer thickness change during applying loads. For flip chip assembly, 97Pb/Sn flip chip bumped devices were successfully assembled on organic substrates with 37Pb/Sn coined flip chip bumps.

• Journal of Welding and Joining
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• v.32 no.3
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• pp.60-67
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• 2014

The ability of electronic packages and assemblies to resist solder joint failure is becoming a growing concern. This paper reports on a study of high speed shear energy of Sn-4.0wt%Ag-0.5wt%Cu (SAC405) solder with different electroless Ni-P thickness, with $HNO_3$ vapor's status, and with various pre-conditions. A high speed shear testing of solder joints was conducted to find a relationship between the thickness of Ni-P deposit and the brittle fracture in electroless Ni-P deposit/SAC405 solder interconnection. A focused ion beam (FIB) was used to polish the cross sections to reveal details of the microstructure of the fractured pad surface with and without $HNO_3$ vapor treatment. A scanning electron microscopy (SEM) and an energy dispersive x-ray analysis (EDS) confirmed that there were three intermetallic compound (IMC) layers at the SAC405 solder joint interface: $(Ni,Cu)_3Sn_4$ layer, $(Ni,Cu)_2SnP$ layer, and $(Ni,Sn)_3P$ layer. The high speed shear energy of SAC405 solder joint with $3{\mu}m$ Ni-P deposit was found to be lower in pre-condition level#2, compared to that of $6{\mu}m$ Ni-P deposit. Results of focused ion beam and energy dispersive x-ray analysis of the fractured pad surfaces support the suggestion that the brittle fracture of $3{\mu}m$ Ni-P deposit is the result of Ni corrosion in the pre-condition level#2 and the $HNO_3$ vapor treatment.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.11a
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• pp.245-246
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• 2008

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.193-215
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• 2003

Fracture Mechanism of Flip Chip Electromigration Failure - Mostly caused by Cathode Depletion at the UBM/Solder Interface Guideline to Increase Electromigration Resistance Material Selection: Sn/Ag(/Cu) > Pb/63Sn Cu UBM > Ni UBM (but, Solder Material combination) UBM Design: thick UBM is preferable (but, Stress Issue) Pad open/UBM size: as large as possible (but, pad size & pitch limit)

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.47-53
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• 2015

The effects of electroless nickel immersion gold (ENIG) and organic solderability preservative (OSP) surface finishes on the in-situ intermetallics reaction and the electromigration (EM) reliability of Sn-3.0Ag-0.5Cu (SAC305) solder bump were systematically investigated. After as-bonded, $(Cu,Ni)_6Sn_5$ intermetallic compound (IMC) was formed at the interface of the ENIG surface finish at solder top side, while at the OSP surface finish at solder bottom side,$ Cu_6Sn_5$ and $Cu_3Sn$ IMCs were formed. Mean time to failure on SAC305 solder bump at $130^{\circ}C$ with a current density of $5.0{\times}10^3A/cm^2$ was 78.7 hrs. EM open failure was observed at bottom OSP surface finish by fast consumption of Cu atoms when electrons flow from bottom Cu substrate to solder. In-situ scanning electron microscope analysis showed that IMC growth rate of ENIG surface finish was much lower than that of the OSP surface finish. Therefore, EM reliability of ENIG surface finish was higher than that of OSP surface finish due to its superior barrier stability to IMC reaction.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.3
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• pp.81-88
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• 2019

In this study, the effects of graphene oxide (GO) addition on electromigration (EM) lifetime of Sn-3.0Ag-0.5Cu Pb-free solder joint between a ball grid array (BGA) package and printed circuit board (PCB) were investigated. After as-bonded, $(Cu,Ni)_6Sn_5$ intermetallic compound (IMC) was formed at the interface of package side finished with electroplated Ni/Au, while $Cu_6Sn_5$ IMC was formed at the interface of OSP-treated PCB side. Mean time to failure of solder joint without GO solder joint under $130^{\circ}C$ with a current density of $1.0{\times}10^3A/cm^2$ was 189.9 hrs and that with GO was 367.1 hrs. EM open failure was occurred at the interface of PCB side with smaller pad diameter than that of package side due to Cu consumption by electrons flow. Meanwhile, we observed that the added GO was distributed at the interface between $Cu_6Sn_5$ IMC and solder. Therefore, we assumed that EM reliability of solder joint with GO was superior to that of without GO by suppressing the Cu diffusion at current crowding regions.

• Korean Journal of Materials Research
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• v.8 no.9
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• pp.807-812
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• 1998

Interfacial reaction and mechanical properties between Sn-Bi-X ternary alloys(X : 2Cu. 2Sb 5In) and Cu-substrate were studied. Cu/solder joints were subjected to aging treatments for up to 60days to see interfacial reaction at $100^{\circ}C$ and then were examined changes of microstructure and interfacial compound by optical microscopy, SEM and EDS. Cu/solder joints were aged to 30days and then loaded to failure at cross head speed of 0.3mm $\textrm{min}^{-1}$ to measure strength and elongation. According to the result of EDS, it is supposed that the soldered interfacial zone was composed of $\textrm{Cu}_{3}\textrm{Sn}$ and $\textrm{Cu}_{6}\textrm{Sn}_{5}$. According to the tensile test of Cu/solder joint, joint strength was decreased by aging treatment. Fractographs of Cu/Sn-Bi solder detailed the effect of aging on fracture behavior. When intermetallic was thin, the fracture occurred through the solder. But as the interfacial intermetallic is thickened, the fracture propagated along the intermetallic/solder interface.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.43-55
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• 2000

In traditional electronic packages the die and the substrate are interconnected with fine wire. Wire bonding technology is limited to bond pads around the peripheral of the die. As the demand for I/O increases, there will be limitations with wire bonding technology. Flip chip technology eliminates the need for wire bonding by redistributing the bond pads over the entire surface of the die. Instead of wires, the die is attached to the substrate utilizing a direct solder connection. Although several steps and processes are eliminated when utilizing flip chip technology, there are several new problems that must be overcome. The main issue is the mismatch in the coefficient of thermal expansion (CTE) of the silicon die and the substrate. This mismatch will cause premature solder Joint failure. This issue can be compensated for by the use of an underfill material between the die and the substrate. Underfill helps to extend the working life of the device by providing environmental protection and structural integrity. Flux residues may interfere with the flow of underfill encapsulants causing gross solder voids and premature failure of the solder connection. Furthermore, flux residues may chemically react with the underfill polymer causing a change in its mechanical and thermal properties. As flip chip packages decrease in size, cleaning becomes more challenging. While package size continues to decrease, the total number of 1/0 continue to increase. As the I/O increases, the array density of the package increases and as the array density increases, the pitch decreases. If the pitch is decreasing, the standoff is also decreasing. This paper will present the keys to successful flip chip cleaning processes. Process parameters such as time, temperature, solvency, and impingement energy required for successful cleaning will be addressed. Flip chip packages will be cleaned and subjected to JEDEC level 3 testing, followed by accelerated stress testing. The devices will then be analyzed using acoustic microscopy and the results and conclusions reported.

• Journal of Applied Reliability
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• v.7 no.2
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• pp.45-55
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• 2007

In this study, two types of fatigue tests were conducted. Firs, cyclic bending tests were performed using the micro-bending tester. Second, thermal fatigue tests were conducted using a pseudo power cycling machine which was newly developed for a realistic testing condition. A three-dimensional finite element analysis model was constructed. A finite element analysis using ABAQUS was performed to extract the applied stress and strain in the solder joints. Creep deformation was dominant in thermal fatigue and plastic deformation was main parameter for bending failure. From the inelastic energy dissipation per cycle versus fatigue life curve, it can be found that the bending fatigue life is longer than the thermal fatigue life.