• Journal of the Korean Institute of Educational Facilities
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• v.15 no.1
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• pp.17-25
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• 2008

As a study on the advancement planning for the telecommunications infrastructure of the educational facilities for the purpose of the proliferation of e-learning, this study was conducted with the intents of preparing for the design guidelines to be considered in the initial stage of an architectural design for applying WLANs(wireless LANs), which play a role as the international standard for next generation of telecommunications, to the educational facilities and of making a proposal for changes of the existing computer rooms according to the appearance of new teaching and learning tools, for example, digital textbooks, and the proliferation of personal information devices. In this study, the design guidelines were made by analyzing the elements to be applied to architecture designs as well as understanding the trend of the cabling, pathways and spaces requirements in the area of telecommunications after examining the relevant international standards, such as ANSI and TIA, etc., in order for applying WLANs to the educational facilities. In addition, a field survey was conducted targeting on the elementary schools in 'C' city in order to suggest a proposal for the improvements of operations and maintenance of the existing computer labs and computers. As the results of analyzing the data from the field study, it was surveyed that the following matters should be urgently improved in order for the schools to be developed as Ubiquitous schools in the future: First, the biggest hold-up is how to maintain the desktop computers well. Second, there are some limitations far the students to use the computers enough due to the lack of the number of computers. Third, the computer education for the students is limited to instructing the students in training themselves only for the functions of each kind of application software.

• KIEAE Journal
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• v.15 no.4
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• pp.85-90
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• 2015

Purpose: In design and planning Building Integrated Photovoltaic(BIPV) system can reduce cost by replacing building facade as construction material such as roofs, outer walls and windows as well as generating electricity. BIPV system should be applied at the early stage of architectural design. However, it is hard to decide whether using BIPV system or not for architects and builders who are not professional at BIPV system because performance of system is considerably influenced by types of module, installation position, installation methods and so on. It is also hard for experts because commercialized analytical program of photovoltaic systems is too complicated to use and domestic meteorological data is limited to partial areas. Therefore, we need evaluation program of BIPV system which can easily but accurately interpret generating performance and evaluate validity of BIPV system at the early stage of architectural design even for inexpert. Method: In this study, we collected meteorological data of domestic major region and analyzed generation characteristic of BIPV system by using PVsyst(commercialized software) in accordance with regions, types of solar module, place and methods of installation and so on. Based on this data, we developed performance evaluation program of BIPV system named BIPV-Pro, through multiple regression analysis and evaluated its validity. Result: When comparing predictive value of annual average PR and annual electricity production of BIPV-Pro an that of PVsyst, each of root mean square error was 0.01897 and 123.9.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.35 no.11
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• pp.1407-1413
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• 2011

In this paper, the structural design for composite blade was performed and full scale structural test was conducted to verify the structural design and integrity of composite blade. Firstly, FE analysis was performed using commercial software ABAQUS under conditions of rated wind speed and Case H in IEC 61400-2. Lay-up sequence and ply thickness were designed based on FE results. And to verify the structural design, full scale structural test was conducted according to IEC 61400-2 under identical loading conditions of FE analysis. Finally, the force-deflection and local strain behavior of composite blade were evaluated.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.167-173
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• 2015

This paper presents a study on the Full-HD HEVC(High Efficiency Video Coding) encoder IP(Intellectual Property) design. The designed IP is for HEVC main profile 4.1, and performs encoding with a speed of 60 fps of full high definition. Before hardware and software design, overall reference model was developed with C language, and we proposed a parallel processing architecture for low-power consumption. And also we coded firmware and driver programs relating IP. The platform for verification of developed IP was developed, and we verified function and performance for various pictures under several encoding conditions by implementing designed IP to FPGA board. Compared to HM-13.0, about 35% decrease in bit-rate under same PSNR was achieved, and about 25% decrease in power consumption under low-power mode was performed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.281-284
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• 2008

This paper describes ASIC design of multimedia SoC Platform. The implemented Platform consists of 32-bit OpenRISC1200 Microprocessor, WISHBONE on-chip bus, VGA Controller, Debug Interface, SRAM Interface and UART. The 32-bit OpenRISC1200 processor has 5 stage pipeline and Harvard architecture with separated instruction/data bus. The VGA Controller can display RCB data on a CRT or LCD monitor. The Debug Interface supports a debugging function for the Platform. The SRAM Interface supports 18-bit address bus and 32-bit data bus. The UART provides RS232 protocol, which supports serial communication function. The Platform is design and verified on a Xilinx VERTEX-4 XC4VLX80 FPGA board. Test code is generated by a cross compiler' and JTAG utility software and gdb are used to download the test code to the FPGA board through parallel cable. Finally, the Platform is implemented into a single ASIC chip using Chatered 0.18um process and it can operate at 100MHz clock frequency.

• Transactions of the Korean Society of Mechanical Engineers
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• v.17 no.6
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• pp.1412-1422
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• 1993

As a part of development of process planning system for mold die manufaturing, a software system is developed, which recognizes features and extracts parameters of the shape from design data produced by solid modeller. The recognized feature date is fed to process planning and operation planning system. Low level geometry and topology data from commercial CAD system is transformed to high level machining feature data which used to be done by using a dedicated design system. The recognition algorithm is applied to the design data with boundary representation produced by a core modeller ACIS which has object oriented open architecture and is expected to become a common core modeller of next generation CAD system. The algoritm of recognition has been formulated for 21 features on prismatic components, but the feature set can be expanded by adding rules for the additional features.

• Journal of KIISE:Software and Applications
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• v.32 no.10
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• pp.963-973
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• 2005

Increasing attention is being recently devoted to various problems inherent in the topological design of networks systems. The topological structure of these networks can be based on service centers, terminals (users), and connection cable. Lately, these network systems are well designed with tiber optic cable, because the requirements from users become increased. But considering the high cost of the fiber optic cable, it is more desirable that the network architecture is composed of a spanning tree. In this paper, we present a GA (Genetic Algorithm) for solving bicriteria network topology design problems of wide-band communication networks connected with fiber optic cable, considering the connection cost, average message delay, and the network reliability We also employ the $Pr\ddot{u}fer$ number (PN) and cluster string in order to represent chromosomes. Finally, we get some experiments in order to certify that the proposed GA is the more effective and efficient method in terms of the computation time as well as the Pareto optimality.

• Journal of KIISE:Software and Applications
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• v.35 no.2
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• pp.91-104
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• 2008

Service-Oriented Computing (SOC) is the development method that published services are selected and composed at runtime to deliver the expected functionality to service clients. SOC should get maximum benefits not only supporting business agility but also reducing the development time. Services are selected and composed at runtime to improve the benefits. However, current programming language, SOC platforms, business process modeling language, and tools support either manual selection or static binding of published services. There is a limitation on reconfiguring and redeploying the business process to deliver the expected services to each client. Therefore, dynamic selection is needed for composing appropriate services to service clients in a quick and flexible manner. In this paper, we propose Dynamic Selection Handler (DSH) on ESB. we present a design method of Dynamic Selection Handler which consists of four components; Invocation Listener, Service Selector, Service Binder and Interface Transformer. We apply appropriate design patterns for each component to maximize reusability of components. Finally, we describe a case study that shows the feasibility of DSH on ESB.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.9
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• pp.459-466
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• 2007

TCP/IP processing imposes a heavy load on the host CPU when it is processed by the host CPU on a very high-speed network. Recently the TCP/IP Offload Engine (TOE), which processes TCP/IP on a network adapter instead of the host CPU, has become an attractive solution to reduce the load in the host CPU. There have been two approaches to implement TOE. One is the software TOE in which TCP/IP is processed by an embedded processor and the other is the hardware TOE in which TCP/IP is processed by a dedicated ASIC. The software TOE has poor performance and the hardware TOE is neither flexible nor expandable enough to add new features. In this paper we designed and implemented a hybrid TOE architecture, in which TCP/IP is processed by cooperation of hardware and software, based on an FPGA that has two embedded processor cores. The hybrid TOE can have high performance by processing time-critical operations such as making and processing data packets in hardware. The software based on the embedded Linux performs operations that are not time-critical such as connection establishment, flow control and congestions, thus the hybrid TOE can have enough flexibility and expandability. To improve the performance of the hybrid TOE, we developed a hardware-based transmission/reception accelerator that processes important operations such as creating data packets. In the experiments the hybrid TOE shows the minimum latency of about $19{\mu}s$. The CPU utilization of the hybrid TOE is below 6 % and the maximum bandwidth of the hybrid TOE is about 675 Mbps.

• International Journal of Naval Architecture and Ocean Engineering
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• v.6 no.2
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• pp.297-306
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• 2014

The paper presents the numerical analysis of wave run-up over rubble-mound breakwaters covered by antifer units using a technique integrating Computer-Aided Design (CAD) and Computational Fluid Dynamics (CFD) software. Direct application of Navier-Stokes equations within armour blocks, is used to provide a more reliable approach to simulate wave run-up over breakwaters. A well-tested Reynolds-averaged Navier-Stokes (RANS) Volume of Fluid (VOF) code (Flow-3D) was adopted for CFD computations. The computed results were compared with experimental data to check the validity of the model. Numerical results showed that the direct three dimensional (3D) simulation method can deliver accurate results for wave run-up over rubble mound breakwaters. The results showed that the placement pattern of antifer units had a great impact on values of wave run-up so that by changing the placement pattern from regular to double pyramid can reduce the wave run-up by approximately 30%. Analysis was done to investigate the influences of surface roughness, energy dissipation in the pores of the armour layer and reduced wave run-up due to inflow into the armour and stone layer.