• Proceedings of the KIPE Conference
• /
• 2016.07a
• /
• pp.459-460
• /
• 2016

본 논문은 분산전원과 베터리에너지저장장치로 구성된 독립형 DC 마이크로그리드에서 배터리 에너지저장장치의 SoC변동에 따른 새로운 출력 전압 제어 방식을 제안하고 동작과 성능을 분석한 내용에 대하여 기술하고 있다. 제안하는 제어 방식은 SoC를 검출하여 일정한 게인 값을 곱하고 그 결과를 기저전압에 더해 DC Grid전압을 산출하는 방식이다. 제안하는 시스템의 동작타당성을 체계적으로 비교 분석하기 위해 PSCAD/EMTDC 소프트웨어를 이용하여 검증하였다. 이를 기반으로 하드웨어 시뮬레이터를 제작하고 실험을 실시하여 실제 독립형 DC 마이크로그리드에 적용 가능성을 확인하였다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.38A no.12
• /
• pp.1145-1147
• /
• 2013

There are two FFT(Fast Fourier Transform) algorithms, which are DIT(Decimation-In-Time) and DIF(Decimation-In- Frequency). Even the DIF algorithm is more widely used because of its various implementation architectures, the DIT structures have not been investigated. In this paper, the DIT Radix-4 algorithm is derived and its efficient butterfly structure is proposed for SoC(System on a Chip) implementation.

• Journal of IKEEE
• /
• v.23 no.4
• /
• pp.1203-1207
• /
• 2019

As the number of IP cores has been increasing in a System-on-Chip (SoC), multiple routers are included in on-chip-networks. Each router has its own arbitration policy and it is difficult to obtain a desired arbitration result by combining multiple routers. Allocating desired bandwidths to the ports across the routers is more difficult. In this paper, a guaranteed bandwidth allocation scheme using an IP-level QoS control is proposed to overcome the limitations of existing local arbitration policies. Each IP can control the priority of a packet depending on the data communication requirement within the allocated bandwidth. The experimental results show that the proposed mechanism guarantees for IPs to utilize the allocated bandwidth in multiple router on-chip-networks. The maximum error rate of bandwidth allocation of the proposed scheme is only 1.9%.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.859-862
• /
• 2003

This paper proposes an emulation environment for SoC designs using small number of large gate-count FPGA's and a PC system. To overcome the pin limitation problem in partitioning the design when the design size overwhelms the FPGA gate count, we use bus splitter modules that replicate on-chip bus signals in one FPGA to arbitrary number of other FPGA's with minimal pin count. The proposed scheme is applied to the emulation of 2 million gate multimedia processing chip using two Xilinx Viretex-2 6000 FPGA devices in 6.6MHz operating frequency. An ARM core, memories, camera and LCD display are modeled in software using dual 2GHz Pentium-III processors. This scheme can be utilized for more than 2 FPGA's in the same ways as two FPGA case without losing emulation speed.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.5
• /
• pp.19-32
• /
• 1997

So far, the multiple path MINs to provide redundant paths in the traditional UPP MINs have been realized by adding additional hardware such as extra stages, duplicated data links, or multiple copies of sthe MIN. And the traditional MINs do not exploit locality: communication with all processor-memory paris takes the same amount of time. Also so far there has been little progress for exploiting locality of reference in MINs. In this paper, we present a new topology MIN, hybrid MIN that is constructed with 2N-3 SEs which is far fewer SEs than that of traditional MINs. Although the hybrid MIN is constructed with 2N-3 SEs, the hybrid MIN satisfies full access capability (FAC) and has redundant paths(but providing single path for 2 memory modules of each processor). Moreover the has redundant paths (but providing single path for 2 memory modules of each processor). Moreover the Hybrid MIN provides shortcut path between pairs which have frequent dat acommunication (locality of reference). Its performance under varing degrees of localized communication is analyzed.

• Proceedings of the KIPE Conference
• /
• 2006.06a
• /
• pp.31-33
• /
• 2006

최근 IT 기술의 발달로 배전자동화 시스템에 많은 통신방식들이 적용되고 있다. 이 중에서 기존 인프라를 사용하는 방식인 전력선통신 기술은 가장 효율적인 통신방식으로 언급되고 있다. 이를 배전자동화 시스템에 적용하기 위해서는 별도의 신호처리 장치와 통신장치가 필요하나, 비용, 설치 및 운영의 불편함으로 확대 적용에 많은 애로점을 가지고 있다. 본 논문에서는 이러한 문제점을 해결하기 위해 SoC 기술을 이용 전력선 통신을 위한 통신 모듈과 고해상도 아나로그 디지털 변환기, 제어용 신호를 처리하는 전용 디지털 신호처리 장치를 결합, 하나의 칩으로 설계하여 경량, 박막화를 실현하였다. 이로 인해 구성부품이 최소화되면서 개발과정이 단축되고, 성능, 전력 소비면에서 유리하며, 다양한 기능을 구비한 전력선통신기반 제어 시스템을 설계할 수 있다.

• Korea Information Processing Society Review
• /
• v.14 no.6
• /
• pp.118-127
• /
• 2007

공정기술의 미세화가 진행될수록 반도체 제품의 개발비용은 급격히 증가 할 것으로 예측되고 있다. 이는 지속적으로 증가하는 설계 복잡도와 미세공정에서 고성능 및 저전력 반도체 구현의 어려움에 의한 것이다. 제품수명기간(Product Life Cycle: PLC)이 점점 짧아지지만 핵심 부품인 반도체 제품의 개발기간과 설계인력은 급격히 증가해감에 따라 늘어만 가는 개발 비용은 반도체 제품의 수익향상 측면에서 매우 큰 장애가 되고 있다. 따라서 설계의 복잡화와 구현의 어려움 이라는 기술적인 문제들을 해결하여 시장에서의 생존이 걸린 극한적인 경쟁환경에서 살아 남기위해서는 반도체 설계의 paradigm 자체를 변화 시켜야 할 것이다. 이에 대한 해법으로 반도체 설계의 abstraction level을 현재의 RTL에서 상위 수준으로 올리고 설계의 virtualization을 해야 한다는 것은 설계 재사용과 신개념 검증 방법 기술과 함께 필수적인 변화의 한 방향이다. 이미 수년전부터 많은 연구 논문에서 이와 관련된 새로운 system 설계 기술들이 제시되어 왔고, 이에 대응하는 platform 기반의 설계기법 소개와 삼성전자의 구축현황에 대해 저자는 지난 논문에서 기술 한 바 있다. 본 논문은 2003년 9월 이후 platform 설계기법의 virtual 화가 어떻게 발전되어 왔는지에 대해 기술하고 문제점 확인 및 앞으로 이에 대한 해결 방안들의 방향에 대해 논하고자 한다.

• Journal of IKEEE
• /
• v.20 no.3
• /
• pp.333-336
• /
• 2016

LIN (local interconnect network) is a standard low-speed serial communication protocol, and it was developed as an efficient sub-bus for automotive electronic modules. In this paper, a LIN controller was implemented in Verilog HDL, based on LIN ver. 2.2A. The implemented LIN controller was verified in FPGA, and it can be supplied as an IP to be integrated into SoC system. Its size is about 2,300 gates when synthesized in 0.18um technology.

• The Journal of Korea Robotics Society
• /
• v.18 no.1
• /
• pp.88-92
• /
• 2023

Lithium-ion batteries are actively used in various industrial sites such as field robots, drones, and electric vehicles due to their high energy efficiency, light weight, long life span, and low self-discharge rate. When using a lithium-ion battery in a field, it is important to accurately estimate the SoC (State of Charge) of batteries to prevent damage. In recent years, SoC estimation using data-based artificial neural networks has been in the spotlight, but it has been difficult to deploy in the embedded board environment at the actual site because the computation is heavy and complex. To solve this problem, neural network lightening technologies such as network pruning have recently attracted attention. When pruning a neural network, the performance varies depending on which layer and how much pruning is performed. In this paper, we introduce an optimized pruning technique by improving the existing pruning method, and perform a comparative experiment to analyze the results.

• Journal of the Korean Institute of Navigation
• /
• v.15 no.3
• /
• pp.53-72
• /
• 1991

The marine cargo insurance compensates the cargo losses that happened during navigation . at the early days of the marine insurance, the insurer inclusively covered all risks that happended during navigation. But since the feature of the risks have been changed due to the development of the shipbuilding technique and commerce, the insurer could not bear all of the perils inclusively. So, the insurer have taken the limitation of the risks insured and the losses paid by exclusion clauses. Therefore, the purpose ;of this paper is to compare the exclusion clauses in the new Institute Cargo Clause (hereafter I.C.C.) with those in the former I.C.C.(all risks, F.P.A) and to make clear the scope of insurer's liability through the theoretical interpretation, clarification of various excluded risks in laws and clauses relating to marine cargo insurance. From what 1 mentioned above, 1 conclude that through continued study on the exclusion sin the new I.C.C., we should organize and establish a system which will satisfy both underwriters and the assured in making the application and the effectiveness equal for each party.