• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.78-85
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• 2008

This paper presents a high-level design methodology applied on an SoC using SystemC. The topic will emphasize on high-level design approach for intensive architecture exploration and verifying cycle accurate SystemC models comparative to real Verilog RTL models. Unlike many high-level designs, we started the poject with working Verilog RTL models in hands, which we later compared our SystemC models to real Verilog RTL models. Moreover, we were able to use the on-chip test board performance simulation data to verify our SystemC-based platform. This paper illustrates that in high-level design, we could have the same accuracy as RTL models but achieve over one hundred times faster simulation speed than that of RTL's. The main topic of the paper will be on architecture exploration in search of performance degradation in source.

• Smart Media Journal
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• v.1 no.1
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• pp.1-9
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• 2012

This Paper proposes an effective SoC hardware architecture implementing a VDP for Full HD TVs. The proposed architecture makes real time video processing possible with supporting efficient bus architecture and flexible interface. Video IP cores in the VDP are designed to provide a high quality of improved image enhancement function. The Avalon interface is adopted to guarantee real-time capability to IPs as well as SoC integration. This leads to reduced design time and also enhanced designer's convenience due to the easiness in IP addition, deletion, and revision for IP verification and SoC integration. The embedded software makes it possible to implement flexible real-time system by controlling setting parameter details and data transmitting schemes in real-time. The proposed VDP SoC design is implemented on Cyclon III SoPC platform. The experimental results show that our proposed architecture of the VDP SoC successfully provides required quality of Video image by converting SD level input to Full HD level image.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.503-506
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• 2015

In accordance with IoT(Internet of Things) commercialization, the need to design SoC-based hardware platform with wireless communication is increasing. This paper therefor proposes an SoC platform architecture with Smart Frame System inter-communicating between devices. Wireless communication functions and high-performance real-time image processing hardware structure was applied to existing digital photo frame. We developed a smart phone application to control the smart frame through Bluetooth communication. The SoC platform hardware consists of CIS controller, Memory controller, ISP(Image Signal Processing) module for image scaling, Bluetooth Interface for inter-communicating between devices, VGA/TFT-LCD controller for displaying video. The Smart Frame System to support the IoT services was implemented and verified using HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA. The operating frequency is 54MHz.

• Journal of Korea Technology Innovation Society
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• v.9 no.4
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• pp.776-795
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• 2006

This paper aims at examining technological catching-up in the Korean IT SoC industry using the theories of technological catching-up and sectoral system of innovation. The Korean IT SoC industry has accomplished rapid technological catching-up by the process of variety generation and selection. In the process, Korean fabless ventures have pursued the technological path-creative pattern in niche markets. But the cooperative networks among various firms are prerequisite for the coevolution of sectoral innovation system.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04d
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• pp.286-288
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• 2003

본 논문에서는 서로 다른 네트워크간의 다양한 프로토콜과 이종의 트래픽을 동시에 처리할 수 있는 네트워크용 SoC (System-on-a-Chip) 프로세서를 구현하였다. 제작된 네트워크 SoC 프로세서는 ARM 프로세서 코어와 ATM(Asynchronous Transfer Mode) 블록, 10/100 Mbps 이더넷 볼록, 스케쥴러, UART 등을 이용하였고 각 블록은 AM8A (Advanced Microcontroller Bus Architecture) 버스로 연결하였다. SoC 프로세서는 CADENCE사의 VerilogHDL을 이용하여 설계하였고 0.35$\mu\textrm{m}$ 셀 라이브러리를 이용하여 검증하였다. 구현된 칩은 총 게이트수가 312,000개이며 칠의 최대 동작 주파수는 50MHz 이다.

• The Journal of the Korea Contents Association
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• v.7 no.11
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• pp.84-93
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• 2007

This paper presents a methodology that accelerates estimating the system-level power consumption for on-chip bus of SoC platforms. The proposed power modeling can estimate the power consumption according to the change of a target SoC system. The proposed model comprises two parts: the one is power estimation of bus logics reflecting the architecture of the bus such as the number of bus layers, the other is to estimate the power consumed by the bus lines during data transmission. We designed the target multimedia SoC system, MPEG encoder as an example and evaluated power consumption using this model. The simulation result shows that the accuracy of the proposed model is over 92%. Thus, the proposed power model can be used to design of a high-performance/low-power multimedia SoC.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.3
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• pp.664-668
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• 2010

This paper presents a System-On-a-chip (SoC) for embedded image processing and pattern recognition applications that need Gaussian Pyramid structure. The system is fully implemented into Field-Programmable Gate Array (FPGA) based on the prototyping platform. The SoC consists of embedded processor core and a hardware accelerator for Gaussian Pyramid construction. The performance of the implementation is benchmarked against software implementations on different platforms.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.05a
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• pp.63-65
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• 2021

This paper describes an integrated H/W-S/W implementation of elliptic curve digital signature algorithm (EC-DSA) using a security system-on-chip (SoC). The security SoC uses the Cortex-A53 APU as CPU, and the hardware IPs of high-performance elliptic curve cryptography (HP-ECC) core and SHA3 (secure hash algorithm 3) hash function core are interfaced via AXI4-Lite bus protocol. The signature generation and verification processes of EC-DSA were verified by the implementation of the security SoC on a Zynq UltraScale+ MPSoC device.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.68-73
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• 2006

This, paper proposes a cosimulation methodology that results in an efficient SoC design as well as fast verification by integrating HDL, SystemC, and algorithm-level abstraction using the design tools Active-HDL and Matlab's Simulink. To demonstrate the proposed design methodology, we implemented the design technique on a serial connection multi-channel speaker system. We have demonstrated the proposed cosimulation method utilizing an ARM processor based SoC Master board with the AMBA bus interface and a Xilinx Vertex4 FPGA. The proposed method has the advantage of simultaneous simulation verification of both software and hardware parts in high levels of abstraction mixed with some performance critical parts in more concrete RTL codes. This allows relatively fast and easy design of a speaker connection system which typically requires significant amount of data processing for verification.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.1-9
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• 2006

In the System-on-Chip(SoC) design, the global wires are critical parts for the performance. Therefore, the global wires need to be pipelined using flip-flops or latches. Since the timing constraint of the latch is more flexible than it of the flip-flop, the latch-based design can provide a better solution for the clock period. Retiming is an optimizing technique which repositions memory elements in the circuits to reduce the clock period. Traditionally, retiming is used on gate-level netlist, but retiming for SoC is used on macro-level netlist. In this paper, we extend the previous work of retiming for SoC using flip-flops to retiming for SoC using single-phase clocked latches. In this paper we propose a MILP for retiming for SoC using single-phase clocked latches, and apply the fixpoint computation to solve it. Experimental results show that retiming for SoC using latches reduces the clock period of circuits by average 10 percent compared with retiming for SoC using flip-flops.