• Journal of Korea Society of Digital Industry and Information Management
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• v.15 no.3
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• pp.1-14
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• 2019

The 4th Industrial Revolution, intelligent automobile application technology is evolving beyond the limit of the mobile device to a variety of application software and multi-media collective technology with big data-based AI(artificial intelligence) technology. with the recent commercialization of 5G mobile communication service, artificial intelligent automobile technology, which is a fusion of automobile and IT technology, is evolving into more intelligent automobile service technology, and each multimedia platform service and application developed in such distributed environment is being developed Accordingly, application software technology developed with a single system SoC of a portable terminal device through various service technologies is absolutely required. In this paper, smart device design for ontology design of intelligent automobile open platform enables to design intelligent automobile middleware software design technology such as Android based SVC Codec and real time video and graphics processing that is not expressed in single ASIC application software technology as SoC based application designWe have experimented in smart device environment through researches, and newly designed service functions of various terminal devices provided as open platforms and application solutions in SoC environment and applied standardized interface analysis technique and proved this experiment.

• Journal of IKEEE
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• v.21 no.3
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• pp.185-194
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• 2017

In this paper, a modular platform for wearable devices is proposed which can be easily assembled by exchanging functions according to various field and environment conditions. The proposed modular platform consists of a 32-bit RISC CPU, a 32-bit symmetric multi-core processor, and a 16-bit DSP. It also includes a plug & play features which can quickly respond to various environments. The sensing and communication modules are connected in the form of a chain. This work is implemented in a standard 130 nm CMOS technology and the proposed modular wearable platforms are verified with temperature and humidity sensors.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.7
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• pp.1418-1423
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• 2009

This paper describes the design and implementation of a System-on-a-Chip (SoC) for image processing applications to use in wearable/mobile products. The target Soc consists of LEON 2 core, AMBA/APB bus-systems and custom-designed controllers. A new FPGA-based prototyping platform is implemented and used for design and verification of the target SoC. To ensure that the implemented SoC satisfies the required performances, an image processing application is performed.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.10
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• pp.2059-2063
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• 2009

This paper presents a programmable System-On-a-chip (SoC) for various embedded smart applications that need Neural Network computations. The system is fully implemented into a prototyping platform based on Field Programmable Gate Array (FPGA). The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using a real image processing application, an optical character recognition (OCR) system.

• 전자공학회논문지 IE
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• v.46 no.4
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• pp.1-7
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• 2009

The final goal of ITS and ETC will be to improve the traffic efficiency and mobile safety without new road construction. DSRC system is emerging nowadays as a solution of them. China DSRC standard which was released in May 2007 has low bit rate, short message and simple MAC control. The DSRC system users want a long lifetime over 1 year with just one battery. In this paper, we propose the SoC of very low power consumption architecture. Several digital logic concept and analog power control logics were used for very low power consumption. The SoC operation mode and clock speed, operation voltage range, wakeup signal detector, analog comparator and Internal Voltage Regulator & External Power Switch were designed. We confirmed that the SoC power consumption is under 8.5mA@20Mhz, 0.9mA@1Mhz in active mode, and under 5uA in power down mode, by computer simulation. The design of SoC was finished on Aug. 2008, and fabricated on Nov. 2008 with $0.18{\mu}m$ CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.84-89
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• 2007

In order to design and test an SoC modem for high speed communication, the platform with the architecture of such high speed communication is needed. That platform is needed for testing large data in speed of 500Mbps. This paper shows that transmission data can be uploaded and downloaded by 250Mbps between a virtual modem target board and a PC through the AHB-PCI IP and the speed of based on DPRAM and PCI.

• Journal of Korea Multimedia Society
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• v.12 no.5
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• pp.617-632
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• 2009

In this paper we propose a technique of implementing the reconfigurable network protocol stack that allows for partitioning network protocol functions into software and hardware tasks on a SoC (System on Chip) platform. Additionally, we present a method that guarantees the deadline of both an individual task and messages exchanging among tasks in order to meet the deadline of real-time multimedia and networking services. The proposed real-time message exchange method guarantees the deadline of messages generated by multimedia services that are required to meet the real-time properties of multimedia applications. After implementing the networking functions of TCP/IP protocol suite into hardware and software tasks, we verify and validate their performance on the SoC platform. Experimental results indicate that the proposed technique improves the performance of TCP/IP protocol suit as well as application service satisfaction in application-specific real-time.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.212-218
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• 2012

A stereo vision is able to build three-dimensional maps of its environment. It can provide much more complete information than a 2D image based vision but has to process, at least, that much more data. In the past decade, real-time stereo has become a reality. Some solutions are based on reconfigurable hardware and others rely on specialized hardware. However, they are designed for their own specific applications and are difficult to extend their functionalities. This paper describes a vision system based on a System on a Chip (SoC) platform. A real-time stereo image correlator is implemented using Sum of Absolute Difference (SAD) algorithm and is integrated into the vision system using AMBA bus protocol. Since the system is designed on a pre-verified platform it can be easily extended in its functionality increasing design productivity. Simulation results show that the vision system is suitable for various real-time applications.

• Journal of Multimedia Information System
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• v.3 no.3
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• pp.85-90
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• 2016

We firstly tried to understand consumers' purchasing tendencies and mainly focused on designing a platform model that offers integrated support. C2B (Customer to Business) orders integrate with a consumption platform of a B2C (Business to Customer) model, and integrated support aims at design, supply, processing, and distribution of a fashion business. All the information such as orders, sales, production, supply, and settlement of accounts is synchronized under the C2B, B2C, and O2O (Online to Offline) environment so that accurate information can be shared in real time. Our platform automatically handles with a net income of a product designer, manufacturer, and shipping company once shipping is confirmed.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.3
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• pp.664-668
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• 2010

This paper presents a System-On-a-chip (SoC) for embedded image processing and pattern recognition applications that need Gaussian Pyramid structure. The system is fully implemented into Field-Programmable Gate Array (FPGA) based on the prototyping platform. The SoC consists of embedded processor core and a hardware accelerator for Gaussian Pyramid construction. The performance of the implementation is benchmarked against software implementations on different platforms.