• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6C
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• pp.498-504
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• 2008

In this paper, an efficient hardware platform for the digital signal processing for OFDM Communication systems is presented. The hardware platform consists of a single FPGA, two DSPs with 8000 MIPS of maximum at 1 GHz clock, 2-channel ADC and DAC supporting maximum 125 MHz sampling rate, and flexible data bus architecture, so that a wide variety of baseband signal processing algorithms for practical OFDM communication systems may be implemented and tested. The IEEE 802.16 software modem is also presented in order to verify the effectiveness and usefulness of the designed platform.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.156-159
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• 2022

There are lots of data-driven analytics approaches to realize smart city. In Korea, Smart City Integration Platform has been deployed in more than 108 cities so It is very important to utilize the platform for smart city. This paper introduces interworking PoC(Proof of Concept) case between Smart City Data Hub, one of the data platform technologies for smart city, and Smart City Integration Platform for enhancing interoperability of city platforms; Smart City Integration Platform sends various city events to Smart City Data Hub and receives predicted city events produced by data analytics in Smart City Data Hub.

• Proceedings of the KIEE Conference
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• 2006.04a
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• pp.255-257
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• 2006

This paper proposed a platform which includes both Network processor and DSP for flexible IED. The Network processor is one of the Intel's IXP4XX Product Line family and the DSP is one of the TI's C6000 family. An embedded Linux is ported in Network processor so that a DSP program can be downloaded to Network processor through ethernet and then downloaded to DSP. Using this method, various algorithms according to IED can be applied to the Network processor board. Maximum ten ADCs can be connected because there is a CPLD between DSP and ADC. That is, the network processor board which can measure maximum 40 channels is implemented. In DSP program, thread and double buffering methods are used not to miss voltage samples. The Network processor board is verified using a method that eight channel voltage signals converted to digital are transmitted to server through both DSP and IXP425.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4B
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• pp.275-280
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• 2002

Wireless communications have been developed time and time to satisfy more demands of users for internet service, mobile communication service and so on. One of infrastructures leading the next generation wireless communication is HAPS(High Altitude Platform Station). This paper analyzed outage probability when a mobile communication system was constructed by using HAPS. First, an approach to evaluate the carrier to interference power ratio' was introduced and results from the analysis were calculated and simulated. from the results, carrier to interference power ratio (C/I) and fading depth (K) had an effect on outage probability; outage probability decreases when K increases far constant C/I or C/l increases for constant K. In addition, when outage probability for a platform with elevation 30 degrees is expanded into it for 24-platforms, outage probability(C/I=9.8dB) was worse because of many interferers relatively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.89-96
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• 2005

In this paper, we propose a customer premise platform for processing multimedia data service on the ATM network. The proposed platform has a specific AAL2 processor that includes AAL2 protocol and scheduler algorithm so as to off-load large potion of burden from host processor and make it easy to process multimedia data from the ATM network in real time compared with conventional platform in which AAL/ATM tasks are processed by software. The ATS scheduler that is implemented based on 2-level time slot ring provides a simple and efficient method for scheduling data of VBR-rt, UBR and CBR traffics. TMS320C5402 DSP is used to process voice-related tasks such as voice compression and voice packet manupulation and AAL2 processor is implemented on $0.35\;{\mu}m$ process line. We implemented the customer premise equipment for VoDSL service and tested the proposed platform on a test bed network. The experimental results show that the proposed equipment has the call success rate of $97\%$ at least and provides voice service of toll-qualify.

• The KIPS Transactions:PartD
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• v.13D no.5 s.108
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• pp.731-740
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• 2006

WIPI is developed by KWISF(Korea Wireless Internet Standardization Forum) and a wireless internet standard platform adopted by TTA. It needs the certification Process for standard specification in order to confirm interoperability. The WIPI is composed of the HAL, the Runtime Engine, and APIs(WIPI-C, WIPI-Java). nl applications are implemented through WIPI APIs that can be finished by themselves or provided essential functions from runtime engine or HAL. Therefore it needs to certify where the problems occur when errors occurred in a application. In this paper we propose the PCT that certifies a WIPI platform's functionality and APIs and the HCT that certifies HAL APIs. Because the PCT reports the final certification results for the platform it is impossible to know where the problems occur when it fails to certify platform. So, it needs to certify the HAL regardless of platform certification.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.9_10
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• pp.485-496
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• 2008

As the complexity of SoC (System-on-Chip) design increases dramatically. traditional system performance analysis and verification methods based on RTL (Register Transfer Level) are no more valid for increasing time-to-market pressure. Therefore a new design methodology is desperately required for system verification in early design stages. and hardware software (HW-SW) cosimulation at TLM (Transaction Level Modeling) level has been researched widely for solving this problem. However, most of HW-SW cosimulators support few restricted ion levels only, which makes it difficult to integrate HW-SW cosimulators with different ion levels. To overcome this difficulty, this paper proposes a multipurpose framework for HW SW cosimulation to provide systematic SoC design flow starting from software application design. It supports various design techniques flexibly for each design step, and various HW-SW cosimulators. Since a platform design is possible independently of ion levels and description languages, it allows us to generate simulation models with various ion levels. We verified the proposed framework to model a commercial SoC platform based on an ARM9 processor. It was also proved that this framework could be used for the performance optimization of an MJPEG example up to 44% successfully.

• Journal of Broadcast Engineering
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• v.10 no.1 s.26
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• pp.77-82
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• 2005

We propose a highly Integrated motion estimation processor (MEP) for efficient video compression in an SoC platform. When compressing video by the standards like MPEG-4 and H.263, the macroblock related functions motion compensation. mode decision, motion vector prediction, and motion vector difference calculation require the frequent intervention of MCU. Thus the proposed MEP incorporates those functions with the motion estimation capability to reduce the number of interrupts to MCU, which can lead to a highly efficient SoC system. For low-power consumption, the proposed MEP can prevent the temporally static area from motion estimation or can skip the half-pel motion estimation for those macroblocks whose modes are decided as INTRA.

• Journal of IKEEE
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• v.24 no.1
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• pp.186-193
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• 2020

In this paper, we propose a multi-threading system to support reconfigurable hardware accelerators on Zynq SoC. We implement high-performance JPEG decoder with reconfigurable 2D IDCT hardware accelerators to achieve maximum performance available on the platform. In this system, up to four reconfigurable hardware accelerators synchronized with SW threads can be dynamically reconfigured to provide adaptive computing capabilities according to the given image resolution and the compression ratio. JPEG decoding is operated using images with resolutions 480p, 720p, 1080p at the compression ratio of 7:1-109:1. We show that significant performance improvements are achieved as the image resolution or the compression ratio increase. For 1080p resolution, the performance improvement is up to 79.11 times with throughput speed of 99 fps at the compression ratio 17:1.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.696-706
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• 2007

Multiprocessor system on chip (MPSoC) platform has set a new innovative trend for the System on Chip (SoC) design. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and un-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future SoC. Most future SoCs will use network architecture and a packet based communication protocol for on chip communication. This paper presents an adaptive wormhole routing with proactive turn prohibition to guarantee deadlock free on chip communication for NOC architecture. It shows a simple muting architecture with five full-duplex, flit-wide communication channels. We provide simulation results for message latency and compare results with those of dimension ordered techniques operating at the same link rates.