• Title/Summary/Keyword: SoC 테스트

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A Study on the Operational Results of SMART Highway Test-bed (스마트하이웨이 테스트베드 운영결과에 대한 고찰)

  • Jin, Goou-Dong;Kim, Sug-Tae;Lee, Soo-Yang;Kim, Chun-Gyung;Park, Ji-Hun
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.14 no.4
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    • pp.27-39
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    • 2015
  • This study addressed the process to construct, operate, verify the test beds, which had been equipped with a variety of core technologies such as WAVE, Road-Radar, Smart Tolling developed by Smart Highway Project. We have met our research goals, but there were limitations to secure the performance and user feedback because of small scale and short operating time. So, we will enhance user safety, convenience and comfort by accumulating and analyzing big data then improving testbeds and related technologies through subsequent research projects for a long time.

Design and Implementation of Co-Verification Environments based-on SystemVerilog & SystemC (SystemVerilog와 SystemC 기반의 통합검증환경 설계 및 구현)

  • You, Myoung-Keun;Song, Gi-Yong
    • Journal of the Institute of Convergence Signal Processing
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    • v.10 no.4
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    • pp.274-279
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    • 2009
  • The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In this paper, verification environments based-on SystemVerilog and SystemC, one is native-code co-verification environment which makes prompt functional verification possible and another is SystemVerilog layered testbench which makes clock-level verification possible, are implemented. In native-code co-verification, HW and SW parts of SoC are respectively designed with SystemVerilog and SystemC after HW/SW partitioning using SystemC, then the functional interaction between HW and SW parts is carried out as one simulation process. SystemVerilog layered testbench is a verification environment including corner case test of DUT through the randomly generated test-vector. We adopt SystemC to design a component of verification environment which has multiple inheritance, and we combine SystemC design unit with the SystemVerilog layered testbench using SystemVerilog DPI and ModelSim macro. As multiple inheritance is useful for creating class types that combine the properties of two or more class types, the design of verification environment adopting SystemC in this paper can increase the code reusability.

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Design of Smart Frame SoC to support the IoT Services (IoT 서비스를 지원하는 Smart Frame SoC 설계)

  • Yang, Dong-hun;Hwang, In-han;Kim, A-ra;Guard, Kanda;Ryoo, Kwang-ki
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2015.10a
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    • pp.503-506
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    • 2015
  • In accordance with IoT(Internet of Things) commercialization, the need to design SoC-based hardware platform with wireless communication is increasing. This paper therefor proposes an SoC platform architecture with Smart Frame System inter-communicating between devices. Wireless communication functions and high-performance real-time image processing hardware structure was applied to existing digital photo frame. We developed a smart phone application to control the smart frame through Bluetooth communication. The SoC platform hardware consists of CIS controller, Memory controller, ISP(Image Signal Processing) module for image scaling, Bluetooth Interface for inter-communicating between devices, VGA/TFT-LCD controller for displaying video. The Smart Frame System to support the IoT services was implemented and verified using HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA. The operating frequency is 54MHz.

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Efficient Test Wrapper Design in SoC (SoC 내의 효율적인 Test Wrapper 설계)

  • Jung, Jun-Mo
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.10 no.6
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    • pp.1191-1195
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    • 2009
  • We present the efficient test wrapper design methodology considering the layout distance of scan chain. To test the scan chains in SoC, the scan chains must be assigned to external TAM(Test Access Mechanism) lines. The scan chains in IP were placed and routed without any timing violation at normal mode. However, in test mode, the scan chains have the additional layout distance after TAM line assignment, which can cause the timing violation of flip-flops in scan chains. This paper proposes a new test wrapper design considering layout distance of scan chains with timing violation free.

Implementation of Area-based stereo algorithm on SoC based on ARM core (ARM platform 기반의 스테레오 비전 SoC 설계)

  • Chang, Ji-Ho;Lee, Ho-Young;Kim, Jun-Seong;Morris, John
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.703-706
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    • 2005
  • 본 논문에서는 스테레오 비전 알고리즘을 ARM9 프로세서를 사용하는 SoC의 IP 개념으로 구현하였다. 구현하고자 하는 스테레오 비전 시스템을 기능에 따라서 하드웨어와 소프트웨어 모듈로 나누어서 성능을 최대화할 수 있도록 설계하였다. SAD correlator는 한 쌍의 이미지에 많은 계산을 필요로 하기 때문에 성능을 우선시하여 하드웨어로 구성하였고, 소프트웨어는 프로세서를 초기화 시키고, 인터럽트 처리와 SAD correlator, TFT-LCD controller, 메모리 등의 하드웨어를 제어하는 역할을 하는 firmware로 구성을 하였다. 메모리에 기저장된 영상정보를 스테레오 비전 알고리즘을 이용한 결과를 외부 TFT-LCD 모듈에서 필요로 하는 포맷에 맞게 변환시켜서 depth map을 출력하는 시스템을 ARM922T 프로세서가 내장된 Altera Excalibur를 target으로 설계하여 테스트 보드에서 정상적으로 동작하는 것을 확인하였다.

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Equalization Digital On-Channel Repeater Part 2 : Field Test Results (등화형 디지털 동일 채널 중계기 Part 2 : 필드 테스트 결과)

  • Park Sung Ik;Lee Yong-Tae;Eum Homin;Seo Jae Hyun;Kim Heung Mook;Kim Seung Won;Lee Soo-In
    • Journal of Broadcast Engineering
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    • v.10 no.2
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    • pp.221-237
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    • 2005
  • This paper presents and analyzes field test results of Equalization Digital On-Channel Repeater (EDOCR) using ATSC(Advanced Television Systems Committee) terrestrial digital TV broadcasting system. In the field test, according to EDOCR On/Off, types of antennas and receivers we measured reception possibility, C/N(Carrier to Noise Ratio), reception power, noise and input margin at each test point. By the field test results, the reception rate of the receiver manufactured in 2004 was $33\%$ when EDOCR is off and directional antenna is used. However, the reception rate was $100\%$ when EDOCR is on. In addition, the noise margin, which determines reception quality was increased at least 6 dB, so that it is capable of constructing SFN(Single Frequency Network) using the EDOCR.

An Efficient Secrete Key Protection Technique of Scan-designed AES Core (스캔 설계된 AES 코아의 효과적인 비밀 키 보호 기술)

  • Song, Jae-Hoon;Jung, Tae-Jin;Jeong, Hye-Ran;Kim, Hwa-Young;Park, Sung-Ju
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.2
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    • pp.77-86
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    • 2010
  • This paper presents an efficient secure scan design technique which is based on a fake key and IEEE 1149.1 instruction to protect secret key from scan-based side channel attack for an Advanced Encryption Standard (AES) core embedded on an System-on-a-Chip (SoC). Our proposed secure scan design technique can be applied to crypto IP core which is optimized for applications without the IP core modification. The IEEE 1149.1 standard is kept, and low area, low power consumption, very robust secret-key protection and high fault coverage can be achieved compared to the existing methods.

SoC Design of Self-Diagnosing Speaker Connection System (자동 고장진단이 가능한 스피커 연결 시스템의 SoC 설계)

  • Song, Moon-Vin;Kwon, Oh-Kyun;Song, The-Hoon;Chung, Yun-Mo
    • The Journal of the Acoustical Society of Korea
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    • v.26 no.6
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    • pp.269-275
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    • 2007
  • Pervasive Multi-channel audio systems are being realized due to advances in digital technology. This paper proposes an efficient system that serially connects individual speakers with bidirectional digital communication capability by means of SoC design. In particular, each speaker can identify the bit stream assigned to the speaker and convert it into analog audio. Furthermore, the speaker can self-diagnose the speaker functionality by utilizing the designed capability to measure frequencies of various square wave test signals. The proposed system running on 200MHz clock yielded restoration of analog output signal with latency of only $500{\mu}s$ compared to directly driving the speakers in a traditional way.

Development and Verification of SoC Platform based on OpenRISC Processor and WISHBONE Bus (OpenRISC 프로세서와 WISHBONE 버스 기반 SoC 플랫폼 개발 및 검증)

  • Bin, Young-Hoon;Ryoo, Kwang-Ki
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.1
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    • pp.76-84
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    • 2009
  • This paper proposes a SOC platform which is eligible for education and application SOC design. The platform, fully synthesizable and reconfigurable, includes the OpenRISC embedded processor, some basic peripherals such as GPIO, UART, debug interlace, VGA controller and WISHBONE interconnect. The platform uses a set of development environment such as compiler, assembler, debugger and RTOS that is built for HW/SW system debugging and software development. Designed SOC, IPs and Testbenches are described in the Verilog HDL and verified using commercial logic simulator, GNU SW development tool kits and the FPGA. Finally, a multimedia SOC derived from the SOC platform is implemented to ASIC using the Magnachip cell library based on 0.18um 1-poly 6-metal technology.

Reliability Analysis of A System Based on the Execution Characteristics of sub-Modules (동작 특성 기반의 시스템 신뢰도 분석)

  • Na, Yun-Ji;Ko, Il-Seok;Cho, Yong-Hwan
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.2C
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    • pp.143-149
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    • 2002
  • Complexity of the hardware system grows larger, the fault testing becomes more difficult. As we divide system into the functional sub-modules and analyze reliability of a sub-modules on the system, We improve the system test performance. And the analysing results help us to set up the effective strategies for the system test. Also describing the system to a formalized sub-modules, we can analyze the logical accuracy and the characteristics of system. So we can predict the reliability of the system based on execution characteristics. In this paper we propose a reliability analysis method of a system based on the execution characteristics of sub-module.