• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.49-53
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• 2002

The Sn-Cu eutectic solder bump formation ($140{\mu}{\textrm}{m}$ diameter, $250{\mu}{\textrm}{m}$ pitch) by electroplating was studied for flip chip package fabrication. The effect of current density and plating time on Sn-Cu deposit was investigated. The morphology and composition of plated solder surface was examined by scanning electron microscopy. The plating thickness increased with increasing time. The plating rate increased generally according to current density. After the characteristics of Sn-Cu plating were investigated, Sn-Cu solder bumps were fabricated on optimal condition of 5A/dm$^2$, 2hrs. Ball shear test after reflow was performed to measure adhesion strength between solder bump and UBM (Under Bump Metallization). The shear strength of Sn-Cu bump after reflow was higher than that of before reflow.

• Journal of Surface Science and Engineering
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• v.36 no.5
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• pp.386-392
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• 2003

The electroplating process for a solder bump which can be applied for a flip chip was studied. Si-wafer was used for an experimental substrate, and the substrate were coated with UBM (Under Bump Metallization) of Al(400 nm)/Cu(300 nm)Ni(400 nm)/Au(20 nm) subsequently. The compositions of the bump were Sn-Cu and eutectic Sn-Pb, and characteristics of two bumps were compared. Experimental results showed that the electroplated thickness of the solders were increased with time, and the increasing rates were TEX>$0.45 <\mu\textrm{m}$/min for the Sn-Cu and $ 0.35\mu\textrm{m}$/min for the Sn-Pb. In the case of Sn-Cu, electroplating rate increased from 0.25 to $2.7\mu\textrm{m}$/min with increasing current density from 1 to 8.5 $A/dm^2$. In the case of Sn-Pb the rate increased until the current density became $4 A/dm^2$, and after that current density the rate maintains constant value of $0.62\mu\textrm{m}$/min. The electro plated bumps were air reflowed to form spherical bumps, and their bonded shear strengths were evaluated. The shear strength reached at the reflow time of 10 sec, and the strength was of 113 gf for Sn-Cu and 120 gf for Sn-Pb.

• Journal of Surface Science and Engineering
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• v.51 no.1
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• pp.47-53
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• 2018

Sn-based lithium-ion batteries have low cost and high theoretical specific capacity. However, one of major problem is the capacity fading caused by volume expansion during lithiation/delithiation. In this study, 3-dimensional foam structure of Cu-Sn alloy is prepared by co-electrodeposition including large free space to accommodate the volume expansion of Sn. The Cu-Sn foam structure exhibits highly porous and numerous small grains. The result of EDX mapping and XPS spectrum analysis confirm that Cu-Sn foam consists of $SnO_2$ with a small quantity of CuO. The Cu-Sn foam structure electrode shows high reversible redox peaks in cyclic voltammograms. The galvanostatic cell cycling performances show that Cu-Sn foam electrode has high specific capacity of 687 mAh/g at a current rate of 50 mA/g. Through SEM observation after the charge/discharge processes, the morphology of Cu-Sn foam structure is mostly maintained despite large volume expansion during the repeated lithiation/delithiation reactions.

• Journal of Surface Science and Engineering
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• v.39 no.6
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• pp.276-281
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• 2006

In order to improve the performance of PPFs (Pre-Plated Frames), a PPF that employed a Cu-Sn alloy instead of conventionally used Ni was developed and then its properties were investigated. It was found that the electoplated Cu-Sn alloy layer was a mixture of uniformly distributed fine crystallites, resulting In better wettability and crack resistance than those of Ni PPF. Moreover, as in Cu/Ni/Pd/Au PPF, migration of copper atoms from the base metal to the top of the Cu/Cu-Sn/Pd/Au PPF surface was not found although the Cu-Sn layer itself contained considerable amount of copper. It was expected that, by using the newly developed Cu-Sn PPF, any possible heat generation and signal interrupt caused by an external electro-magnetic field could be reduced because the Cu-Sn layer was paramagnetic, i.e., nonmagnetic.

• Korean Journal of Metals and Materials
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• v.46 no.1
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• pp.33-38
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• 2008

The interfacial reactions and shear strength of pure Sn solder bump were investigated with different under bump metallizations (UBMs) and reflow numbers. Two different UBMs were employed in this study: Cu and Ni. Cu6Sn5 and Cu3Sn intermetallic compounds (IMCs) were formed at the bump/Cu UBM interface, whereas only a Ni3Sn4 IMC was formed at the bump/Ni UBM interface. These IMCs grew with increasing reflow number. The growth of the Cu-Sn IMCs was faster than that of the Ni-Sn IMC. These interfacial reactions greatly affected the shear properties of the bumps.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.49-53
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• 2011

High-speed Cu filling into a through-silicon-via (TSV) and simplification of bumping process by electroplating for three dimensional stacking of Si dice were investigated. The TSV was prepared on a Si wafer by deep reactive ion etching, and $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to increase the filling rate of Cu into the via, a periodic-pulse-reverse wave current was applied to the Si chip during electroplating. In the bumping process, Sn-3.5Ag bumping was performed on the Cu plugs without lithography process. After electroplating, the cross sections of the vias and appearance of the bumps were observed by using a field emission scanning electron microscope. As a result, voids in the Cu-plugs were produced by via blocking around via opening and at the middle of the via when the vias were plated for 60 min at -9.66 $mA/cm^2$ and -7.71 $mA/cm^2$, respectively. The Cu plug with a void or a defect led to the production of imperfect Sn-Ag bump which was formed on the Cu-plug.

• Korean Journal of Materials Research
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• v.12 no.3
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• pp.225-230
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• 2002

Sn was selected as an alloying element of Cu. The Cu-Sn thin layers were deposited on the Si substrates by the electroplating method and their properties were studied. By rapidly thermal annealing(RTA) up to 40$0^{\circ}C$ after electroplating, sheet resistance decreased and adhesion strength increased, but that trend was reversed at the 50$0^{\circ}C$ RTA. Cu-Sn particles grew dense and the surface was uniform up to 40$0^{\circ}C$, but at 50$0^{\circ}C$, empty area was introduced and the surface became rough owing to oxidation and particle coarsening and agglomeration. Deposited layer contained significant amount of Si, while pure Cu-Sn layer with the composition ratio of 90:10 was present only on the top surface. However, no significant change in the Cu composition within alloy layers occured by the RTA regardless of its temperature. This indicates that the Cu diffusion into the Si was suppressed by the presence of Sn.

• Proceedings of the KWS Conference
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• 2004.05a
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• pp.84-86
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• 2004

기존의 전자산업에서는 Sn-37Pb 공정솔더를 사용하였으나, 최근 납의 환경적인 문제로 인하여 무연 솔더에 관한 연구와 적용이 세계적으로 진행되고 있다. 무연 솔더의 실용화와 관련하여 Sn-37Pb 솔더와 같은 만능의 솔더는 없지만, 그 중 도입이 가장 유력시 되는 것으로 Sn-Ag-Cu계 솔더가 있다. (중략)

• Journal of Welding and Joining
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• v.31 no.3
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• pp.17-21
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• 2013

Sn whiskers are one of the serious causes of the failure of electronics. Sn whiskers grow spontaneously from Sn-based, lead-free finished surfaces, even at room temperature. A primary factor of these Sn whiskers growth is compressive stress, which enhances the diffusion of Sn or other elements. The sources of compressive stress are the growth of non-uniform large intermetallic compounds along the interface between the Sn grain boundary and Cu substrate. Recent studies revealed the methods for reducing Sn whisker growth. This paper gives an overview about recent researches for mitigation methods of Sn whisker growth during nearly room temperature storage.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.4
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• pp.23-29
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• 2000

We demonstrate the fabrication method of high-density and high-quality solder bump solving a copper (Cu) cross-contamination in Si-LSI laboratory. The Cu cross-contamination is solved by separating solder-bump process by two steps. Former is via-formation process excluding Cu/Ti under ball metallurgy (UBM) layer sputtering in Si-LSI laboratory. Latter is electroplating process including Ti-adhesion and Cu-seed layers sputtering out of Si-LSI laboratory. Thick photoresist (PR) is achieved by a multiple coating method. After TiW/Al-electrode sputtering for electroplating and via formation in Si-LSI laboratory, Cu/Ti UBM layer is sputtered on sample. The Cu-seed layer on the PR is etched during Cu-electroplating with low-electroplating rate due to a difference in resistance of UBM layer between via bottom and PR. Therefore Cu-buffer layer can be electroplated selectively at the via bottom. After etching the Ti-adhesion layer on the PR, Sn/Pb solder layer with a composition of 60/40 is electroplated using a tin-lead electroplating bath with a metal stoichiometry of 60/40 (weight percent ratio). Scanning electron microscope image shows that the fabricated solder bump is high-uniformity and high-quality as well as symmetric mushroom shape. The solder bumps with even 40/60 $\mu\textrm{m}$ in diameter/pitch do not touch during electroplating and reflow procedures. The solder-bump process of high-uniformity and high-density with the Cu cross-contamination free in Si-LSI laboratory will be effective for electronic microwave application.