• Smart Structures and Systems
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• v.8 no.1
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• pp.39-52
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• 2011

We are developing a biomimetic robot based on the Sea Lamprey. The robot consists of a cylindrical electronics bay propelled by an undulatory body axis. Shape memory alloy (SMA) actuators generate propagating flexion waves in five undulatory segments of a polyurethane strip. The behavior of the robot is controlled by an electronic nervous system (ENS) composed of networks of discrete-time map-based neurons and synapses that execute on a digital signal processing chip. Motor neuron action potentials gate power transistors that apply current to the SMA actuators. The ENS consists of a set of segmental central pattern generators (CPGs), modulated by layered command and coordinating neuron networks, that integrate input from exteroceptive sensors including a compass, accelerometers, inclinometers and a short baseline sonar array (SBA). The CPGs instantiate the 3-element hemi-segmental network model established from physiological studies. Anterior and posterior propagating pathways between CPGs mediate intersegmental coordination to generate flexion waves for forward and backward swimming. The command network mediates layered exteroceptive reflexes for homing, primary orientation, and impediment compensation. The SBA allows homing on a sonar beacon by indicating deviations in azimuth and inclination. Inclinometers actuate a bending segment between the hull and undulator to allow climb and dive. Accelerometers can distinguish collisions from impediment to allow compensatory reflexes. Modulatory commands mediate speed control and turning. A SBA communications interface is being developed to allow supervised reactive autonomy.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.1
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• pp.47-54
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• 2003

New efficiency enhancement techniques have been devised and implemented to InGaP/GaAs HBT MMIC power amplifiers for W-CDMA mobile terminals applications. Two different types of bias current control circuits that select the efficient quiescent currents in accordance with the required output power levels are proposed for overall power efficiency improvement. A dual chain power amplifier with single matching network composed of two different parallel-connected power amplifier is also introduced. With these efficiency enhancement techniques, the implemented MMIC power amplifiers presents power added efficiency (PAE) more than 14.8 % and adjacent channel leakage ratio(ACLR) lower than -39 dBc at 20 dBm output power and PAE more than 39.4% and ACLR lower than -33 dBc at 28 dBm output power. The average power usage efficiency of the power amplifier is improved by a factor of more than 1.415 with the bias current control circuits and even up to a factor of 3 with the dual chain power amplifier.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.9
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• pp.911-915
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• 2004

In this study, the electrical characteristics of high-voltage LDMOSFET fabricated by the existing CMOS technology were investigated depending on its process and design parameter. In order to verify the experimental data, two-dimensional device simulation was carried out simultaneously. The off- state breakdown voltages of n-channel LDMOSFETs were increased nearly in proportional to the drift region length. For the case of decreasing n-well ion implant doses from $1.0\times{10}^{13}/cm^2$ to $1.0\times{10}^{12}/cm^2$, the off-state breakdown voltage was increased approximately two times. The on-resistance was also increased about 76 %. From 2-D simulation, the increase in the breakdown voltage was attributed to a reduction in the maximum electric field of LDMOS imolanted with low dose as well as to a shift toward n+ drain region. Moreover, the on- and off-state breakdown voltages were also linearly increased with increasing the channel to n-tub spacing due to the reduction of impact ionization at the drift region. The experimental and design data of these high-voltage LDMOS devices can widely applied to design smart power ICs with low-voltage CMOS control and high-voltage driving circuits on the same chip.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.991-992
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• 2006

Multiprocessor system is efficient and high performance architecture to overcome a limitation of single core SoC. In this paper, we propose a multiprocessor SoC (MPSoC) architecture which provides the low complexity and the high performance. The dynamic routing scheme has a serious problem in which the complexity of routing increases exponentially. We solve this problem by making a cluster with several PEs (Processing Element). In inter-cluster network, we use deterministic routing scheme and in intra-cluster network, we use dynamic routing scheme. In order to control the hierarchical network, we propose efficient router architecture by using smart crossbar switch. We modeled 2-D mesh topology and used simulator based on C/C++. The results of this routing scheme show that our approach has less complexity and improved throughput as compared with the pure deterministic routing architecture and the pure dynamic routing architecture.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.2
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• pp.71-77
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• 2015

Upcoming ground-breaking applications for always-on tiny interconnected devices steadily demand two-fold features of processor cores: aggressively low power consumption and enhanced performance. We propose implementation of a novel superscalar low-power processor core with a low supply voltage. The core implements intra-core low-power microarchitecture with minimal performance degradation in instruction fetch, branch prediction, scheduling, and execution units. The inter-core lockstep not only detects malfunctions during low-voltage operation but also carries out software-based recovery. The chip incorporates a pair of cores, high-speed memory, and peripheral interfaces to be implemented with a 65nm node. The processor core consumes only 24mW at 350MHz and 0.68V, resulting in power efficiency of $80{\mu}W/MHz$. The operating frequency of the core reaches 850MHz at 1.2V.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.10
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• pp.1529-1534
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• 2013

Since a NAND-flash memory is able to store mass data in a small sized chip and consumes low power, it is exploited on various hand-held devices, such as a smart phone and a sensor node, etc. To process efficiently mass data stored in the flash memory, it is required to use an index. However, since the write operation of the flash memory is slower than the read operation and an overwrite operation is not supported, the usage of existing index schemes degrades the performance of the index. In this paper, we survey the previous researches of index schemes for the flash memory and classify the researches by the methods to solve problems. We also present the performance factor to be considered when we design the index scheme on the flash memory.

• Journal of Satellite, Information and Communications
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• v.7 no.2
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• pp.54-58
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• 2012

In this paper, we implemented total monitoring system in which LED light turned on only when user detected and LED light turned out only when user disappeared. This system is composed of two modules, one is HW board based on Micro Controller and the other is SW control system based on Web server. Micro controller board is based on ATMega2560 chip which is connected with Infra Red and Ultra sonic sensors. Web based monitoring system was designed can be used in smart device. The validity of this monitoring system was proved by integration test of two modules.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.347-348
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• 2007

On-chip micro humidity sensor, using $CN_x$ films for the sensing material, was designed, simulated, and fabricated with Op amp based readout circuit and diode temperature sensors. To compensate the temperature and other gases, two methods were applied. One is wheatstone-bridge with reference FET that eliminates other undesirable chemical species, and the other is a diode temperature sensor to compensate the temperature effect. $CN_x$ film can be a new humidity sensing material, and has a strong potential to adapt to smart sensors or multi-sensors using MEMS or nano-technology. A particular design technology for integration of sensors and systems together was proposed that whole fabrication process could be achieved by a standard CMOS process.

• Smart Structures and Systems
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• v.6 no.5_6
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• pp.689-709
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• 2010

In this paper, a low cost, low power but multifunctional wireless sensor node is presented for the impedance-based SHM using piezoelectric sensors. Firstly, a miniaturized impedance measuring chip device is utilized for low cost and low power structural excitation/sensing. Then, structural damage detection/sensor self-diagnosis algorithms are embedded on the on-board microcontroller. This sensor node uses the power harvested from the solar energy to measure and analyze the impedance data. Simultaneously it monitors temperature on the structure near the piezoelectric sensor and battery power consumption. The wireless sensor node is based on the TinyOS platform for operation, and users can take MATLAB$^{(R)}$ interface for the control of the sensor node through serial communication. In order to validate the performance of this multifunctional wireless impedance sensor node, a series of experimental studies have been carried out for detecting loose bolts and crack damages on lab-scale steel structural members as well as on real steel bridge and building structures. It has been found that the proposed sensor nodes can be effectively used for local wireless health monitoring of structural components and for constructing a low-cost and multifunctional SHM system as "place and forget" wireless sensors.

• Smart Structures and Systems
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• v.6 no.5_6
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• pp.661-673
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• 2010

This paper presents recent developments in an extremely compact, wireless impedance sensor node (the WID3, $\underline{W}$ireless $\underline{I}$mpedance $\underline{D}$evice) for use in high-frequency impedance-based structural health monitoring (SHM), sensor diagnostics and validation, and low-frequency (< ~1 kHz) vibration data acquisition. The WID3 is equipped with an impedance chip that can resolve measurements up to 100 kHz, a frequency range ideal for many SHM applications. An integrated set of multiplexers allows the end user to monitor seven piezoelectric sensors from a single sensor node. The WID3 combines on-board processing using a microcontroller, data storage using flash memory, wireless communications capabilities, and a series of internal and external triggering options into a single package to realize a truly comprehensive, self-contained wireless active-sensor node for SHM applications. Furthermore, we recently extended the capability of this device by implementing low-frequency analog-to-digital and digital-to-analog converters so that the same device can measure structural vibration data. The compact sensor node collects relatively low-frequency acceleration measurements to estimate natural frequencies and operational deflection shapes, as well as relatively high-frequency impedance measurements to detect structural damage. Experimental results with application to SHM, sensor diagnostics and low-frequency vibration data acquisition are presented.