• Proceedings of the IEEK Conference
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• 2002.06d
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• pp.171-174
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• 2002

This paper presents an implementation method of phasor measurement device, which is based on the FPGA implementation of the sliding-DFT The design is verified by the timing simulation of its operation. The error effect of coefficient approximation and frequency deviation in the recursive implementation of the sliding-DFT is analytically derived and verified with the computer simulations.

• Journal of Power Electronics
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• v.14 no.3
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• pp.564-571
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• 2014

Rotor initial position is an important factor affecting the control performance of electrically excited synchronous motors. This study presents a novel method for estimating rotor initial position based on sliding discrete Fourier transform (sDFT). By injecting an ac excitation into the rotor winding, an induced voltage is generated in stator windings. Through this voltage, the stator flux can be obtained using a pure integral voltage model. Considering the influence from a dc bias and an integral initial value, we adopt the sDFT to extract the fundamental flux component. A quadrant identification model is designed to realize the accurate estimation of the rotor initial position. The sDFT and high-pass filter, DFT, are compared in detail, and the contrast between dc excitation and ac injection is determined. Simulation and experimental results verify that this type of novel method can eliminate the influence of dc bias and other adverse factors, as well as provide a basis for the control of motor drives.

• Proceedings of the KIEE Conference
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• 2001.07a
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• pp.302-304
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• 2001

본 논문에서는 다 채널 위상 측정 장치를 전용하드웨어로 구현하기 위한 설계 구조에 대하여 제시하였으며, 연산량이 많은 곱셈기를 시분할에 의해 공유하는 구조를 제시하였다. 또한 페이저 측정을 위한 Sliding-DFT 알고리즘을 순환 구현할 경우의 근사 구현 오차에 관한 정량적인 연구를 수행하였다. 이러한 오차 영향의 해석을 기반으로 하여 곱셈기 공유 구조를 적용한 위상 측정 장치를 설계하고, 설계한 하드웨어의 내부동작을 보여주는 시뮬레이션을 통해 설계의 정확성을 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.37 no.4
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• pp.65-71
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• 2000

Finite wordlength effect of the recursive implementation of SDFT(sliding-DFT) is analytically derived in this paper. Representation errors of the twiddle coefficients and the data registers are the two major causes of the spectral errors in the recursive implementation. The noise-to-signal ratio is analytically derived in terms of the coefficients wordlength, the data registers wordlength, and the DFT's block-length used in the computation Error dynamic equation is obtained from the recursive DFT and the probabilistic models for the coefficients error and the round-off error are introduced for the NSR derivation, The result of the NSR derivation is verified with the simulation data.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.436-438
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• 2005

본 논문에서는 전력선 위상 측정을 위해 A/D 변환기 및 위상계측 연산장치를 집적한 하이브리드 센서칩의 구현 기법을 제시하였다. 개발한 위상계측 연산장치는 recursive sliding-DFT에 기반하였으며 곱셈기의 시분할 공유 구조를 사용하여 칩의 구현 면적을 최소화 하였다. 60Hz의 전력선 신호를 중심주파수로 하는 AD 변환장치는 sigma-delta ADC를 기반으로 하여 8-bit 정밀도를 제공하며 아날로그부의 구현을 최소화하도륵 설계하였다. 설계한 하이브리드 센서칩은 컴퓨터 시뮬레이션 및 FPGA 구현을 통해 동작을 검증하였으며, 검증 완료후 $0.35{\mu}m$ CMOS 공정기술로 구현하였다. 전력선 위상을 측정하기 위해 구현된 4채널 하이브리드 센서 칩의 설계면적은 $5{\times}5m^2$ 의 약 20%정도를 차지하였다.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.5
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• pp.96-103
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• 1999

본 논문에서는 sliding-DFT(SDFT)를 계수의 유한 비트 근사구현에 기초하여 실시간 구현하는 기법을 제시하고, 이의 오차영향을 해석하였다. 오차의 영향을 오차전력과 신호전력비율(noise-to-signal power ratio : NSR)로 하여 이를 해석적으로 유도하였다. 가우스 렌덤신호 및 사람의 수면 EEG 신호를 대상으로 수행한 시뮬레이션 결과가 해석식과 잘 일치하는 것을 보임으로써 본 연구에서 얻은 해석식을 확인하였다.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.388-390
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• 2006

This paper presents a hybrid SoC design for phase detection of single tone signal. The designed hybrid SoC is composed of three functional blocks, i.e., an analog to digital converter module, a phase detection module and a controller module. A design of the controller module is based on a 16-bit RISC architecture. An I/O interface and an LCD control interface for transmission and display of phase measurement values are included in the design of the controller module. A design of the phase detector is based on a recursive sliding-DFT. The recursive architecture effectively reduces the gate numbers required in the implementation of the module. The ADC module includes a single-bit second-order sigma-delta modulator and a digital decimation filter. The decimation filter is designed to give 98dB of SNR for the ADC. The effective resolution of the ADC is enhanced to 98dB of SNR by the incorporation of a pre FIR filter, a 2-stage cascaded integrator- comb(CIC) filter and a 30-tab FIR filter in the decimation. The hybrid SoC is verified in FPGA and implemented in 0.35 CMOS Technology.

• Journal of Power Electronics
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• v.10 no.2
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• pp.203-209
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• 2010

This paper describes the development of a three-phase line-interactive DVR with a new sag detection algorithm. The developed detection algorithm has a hybrid structure composed of an instantaneous detector and RMS-variation detectors. The source voltage passes through the sliding-window DFT and RMS calculator, and the instantaneous sag detector. If an instantaneous sag is detected, the RMS variation detector-1 is selected to calculate the RMS variation. The RMS variation detector-2 is selected when the instantaneous sag occurs under the operation of the RMS variation detector-1. The feasibility of the proposed algorithm is verified through computer simulations and experimental work with a prototype of a line-interactive DVR with a 3kVA rating. The line-interactive DVR with the proposed algorithm can compensate for an input voltage sag or an interruption within a 2ms delay. The developed DVR can effectively compensate for a voltage sag or interruption in sensitive loads, such as computers, communications equipment, and automation equipment.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.497-500
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• 2005

This paper presents a design of a hybrid sensor chip which integrates an A/D converter module and a phase measurement module for measuring power line phase. Recursive sliding DFT based phase measurement module is designed using time shared multiplier which can reduce the size of SoC implementation. A/D converter is based on the sigma delta modulation in order to minimize the implementation space of the analog part and designed to obtain 8-bit resolution. Computer simulations and FPGA implementation are performed to verify hybrid sensor chip design. The hybrid sensor chip for 4-channel power line phase measurement is fabricated by using 0.35 micrometer CMOS process.