• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.7
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• pp.440-448
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• 2014

A $4{\times}10$ Gb/s Transimpedance Amplifier (TIA) array is implemented in $0.13{\mu}m$ CMOS process technology, which will be used in the receiver of TWDM-PON system. A technology for bandwidth enhancement of a given $4{\times}10$ Gb/s TIA presented under inductor peaking technology and a single 1.2V power supply based low voltage design technology. It achieves 3 dB bandwidth of 7 GHz in the presence of a 0.5 pF photodiode capacitance. The trans-resistance gain is $50dB{\Omega}$, while 48 mW/ 1channel from a 1.2 V supply. The input sensitivity of the TIA is -27 dBm. The chip size is $1.9mm{\times}2.2mm$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.1
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• pp.81-88
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• 2011

A real time monitoring system from a PC has been developed which can be accessed through transmitted data, which incorporates an established low powered transport system equipped with a single chip combined with wireless sensor network technology from a three-axis acceleration sensor. In order to distinguish between static posture and dynamic posture, the extracted parameter from the rapidly transmitted data needs differentiation of movement and activity structures and status for an accurate measurement. When results interpret a static formation, statistics referring to each respective formation, known as the K-mean algorithm is utilized to carry out a determination of detailed positioning, and when results alter towards dynamic activity, fuzzy algorithm (fuzzy categorizer), which is the relationship between speed and ISVM, is used to categorize activity levels into 4 stages. Also, the ISVM is calculated with the instrumented acceleration speed on the running machine according to various speeds and its relationship with kinetic energy goes through correlation analysis. With the evaluation of the proposed system, the accuracy level stands at 100% at a static formation and also a 96.79% accuracy with kinetic energy and we can easily determine the energy consumption through the relationship between ISVM and kinetic energy.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.77-83
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• 2009

In this paper, a selective feedback low-noise amplifier (LNA) has been realized in a $0.18{\mu}m$ CMOS technology to cover a number of wireless multi-standards. By exploiting notch filter, the SF-LNA demonstrates the measured results of the power gain (S21) of 11.5~13dB and the broadband input/output impedance matching of less than -10dB within the frequency bands of 820~960MHz and 1.5~2.5GHz, respectively. The chip dissipates 15mW from a single 1.8V supply, and occupies the area of $1.17\times1.0mm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.70-79
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• 2016

This paper proposes a low-power range-scaled 14b 30 MS/s pipeline-SAR composite ADC for high-performance CIS applications. The SAR ADC is employed in the first stage to alleviate a sampling-time mismatch as observed in the conventional SHA-free architecture. A range-scaling technique processes a wide input range of 3.0VP-P without thick-gate-oxide transistors under a 1.8 V supply voltage. The first- and second-stage MDACs share a single amplifier to reduce power consumption and chip area. Moreover, two separate reference voltage drivers for the first-stage SAR ADC and the remaining pipeline stages reduce a reference voltage disturbance caused by the high-speed switching noise from the SAR ADC. The measured DNL and INL of the prototype ADC in a $0.18{\mu}m$ CMOS are within 0.88 LSB and 3.28 LSB, respectively. The ADC shows a maximum SNDR of 65.4 dB and SFDR of 78.9 dB at 30 MS/s, respectively. The ADC with an active die area of $1.43mm^2$ consumes 20.5 mW at a 1.8 V supply voltage and 30 MS/s, which corresponds to a figure-of-merit (FOM) of 0.45 pJ/conversion-step.

• Asian Pacific Journal of Cancer Prevention
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• v.15 no.17
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• pp.7333-7336
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• 2014

Human papillomavirus (HPV) infection has been implicated as a causative of cervical cancer. In the present study, a total of 578 samples from females attending the gynecological outpatient clinic in Henan province, China, were collected and the HPV genotypes were detected by gene chip and flow-through hybridization. Overall, 44.5% (257/578) females were found to be HPV DNA positive, and the high risk HPV (HR-HPV) rate was 35.1% (203/578). The first peak of HR-HPV infection appeared in the >60 year-old group (55.0%), and the second was within the 51-55 year-old group (50.0%) (${\chi}^2$=19.497, p<0.05). HPV 16 was the most prevalent genotype (9.2%), followed by HPV 52 (7.8%), HPV 6 (6.9%), HPV 11 (5.9%) and HPV 42 (5.0%). The single type HPV infection was 30.4%, with the five majority prevalent genotype HPV 16 (16.5%), HPV 52 (14.3%), HPV 6 (12.6%), HPV 42 (8.6%), HPV 31 (5.1%). The multiple-type HPV infections were 14.0%, and HPV 16 was the most prevalent type (29.6%), followed by HPV 52 (24.7%), HPV 6 (22.2%), HPV 11 (22.2%), HPV 42 (17.3%) and HPV 39 (17.3%).

• Journal of IKEEE
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• v.17 no.3
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• pp.267-274
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• 2013

This paper presents a design of LLC resonant converter IC for LED backlight unit based on PFM/PWM dual-mode feedback. Dual output LLC resonant architecture with a single inductor is proposed, where the master output is controlled by the PFM and slave output is controlled by the PWM. To regulate the master output PFM is used as feedback to control the frequency of the power switch. On the other hand, PWM feedback is used to control the pulse width of the power switch and to regulate the slave output. This chip is fabricated in 0.35um 2P3M BC(Bipolar-CMOS-DMOS) Process and the die area is $2.3mm{\times}2.2mm$. Current consumptions is 26mA from 5V supply.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.6
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• pp.1-8
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• 1998

This paper presents an asynchronous DS/CDMA multiuser detector, which is a two stage, symbol-by-symbol scheme consisting of conventional detectors followed by linear decorrelating detectors. The conventional detector first makes temporal decisions and the detected symbols are delayed by one symbol period to be used for the selection of decorrelating bases in the subsequent decorrelaing detection stage. It also employs a bank of early-late correlators in place of a bank of single correlators taking the small offset of chip timing asynchronism into account. The proposed detector requires only the coarse knowledge of relative time delays of interfering users and is suitable for digital implementation. To verify the detector performance, the analytical BER performance will be given and compared with the simulation results for BPSK DS/CDMA signals in AWGN channel. While the performance of the proposed detector will be analyzed for time-limited signal, the simulation is carried out for both the time-limited and band-limited signals. As can be seen in the simulation results, the proposed scheme shows good results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.20-25
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• 2010

An integrated Mach-Zehnder interferometric sensor operating at 632.8 nm was designed and fabricated by the technology of planar rib waveguides. Rib waveguide based on silica system ($SiO_2-SiO_xN_y-SiO_2$) was geometrically designed to have single mode operation and high sensitivity. It was structured by semiconductor fabrication processes such as thin film deposition, photolithography, and RIE (Reactive Ion Etching). With the power observation, propagation loss measurement by cut-back method showed about 4.82 dB/cm for rib waveguides. Additionally the chromium mask process for an etch stop was employed to solve the core damaging problem in patterning the sensing zone on the chip. Refractive index measurement of water/ethanol mixture with this device finally showed a sensitivity of about $\pi$/($4.04{\times}10^{-3}$).

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.8
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• pp.79-85
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• 2004

In this paper, the RF-ID system for ubiquitous tagging applications has been designed, fabricated and analysed. The RF-ID System consists of passive RF-ID Tag and Reader. The passive RF-ID tag consists of rectifier using zero-bias schottky diode which converts RF power into DC power, ID chip, ASK modulator using bipolar transistor and slot loop antenna. We suggest an ASK undulation method using a bipolar transistor to compensate the disadvantage of the conventional PIN diode, which needs large current Also, the slot loop antenna with wider bandwidth than that of the conventional patch antenna is suggested The RF-ID reader consist of patch array antenna, Tx/Rx part and ASK demodulator. We have designed the RF-ID System using EM and circuit simulation tools. According to the measured results, The power level of modulation signal at 1 m from passive RF-ID Tag is -46.76 dBm and frequency of it is 57.2 KHz. The transmitting power of RF-ID reader was 500 mW

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.5
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• pp.542-546
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• 2008

Recently dual-port SDRAM (DPSDRAM) architecture tailored for dual-processor based mobile embedded systems has been announced where a single memory chip plays the role of the local memories and the shared memory for both processors. In order to maintain memory consistency from simultaneous accesses of both ports, every access to the shared memory should be protected by a synchronization mechanism, which can result in substantial access latency. We propose two optimization techniques by exploiting the communication patterns of target applications: lock-priority scheme and static-copy scheme. Further, by dividing the shared bank into multiple blocks, we allow simultaneous accesses to different blocks thus achieve considerable performance gain. Experiments on a virtual prototyping system show a promising result - we could achieve about 20-50% performance gain compared to the base DPSDRAM architecture.