• The Journal of Korean Institute of Communications and Information Sciences
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• v.10 no.5
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• pp.209-217
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• 1985

Using the Reed-Muller Codes, the encoder and decoder system has been designed and tested in this paper. The error correcting capability of this code is [J/2} or less and the error correcting procedure can be implemented easily by using simple logic circuitry. The encoding and decoding circuits are obtained by the cyclic property and for the O15, 11) Reed-Muller code majority-logic decoding is taken. The performance is measured in error probability and weight destribution. The encoder and decoder system has been designed, implemented and interfaced with the microcomputer by using the 8255 chip. Experimental results show that the system has single error-correcting capability and total execution time for a data is about 70usec. When the probability of channel error is $10^{-6}$~$10^{-4}$ the system using the (15, 11) Reed-Muller code works very good.

• Journal of Advanced Navigation Technology
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• v.1 no.1
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• pp.23-34
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• 1997

A multi-channel digital GPS receiver has been developed including a RF-to-IF engine (engine 1), a digital signal processing engine (engine 2) with a microprocessor interfacing, and a navigation software. A high speed SiGe heterojunction bipolar transistor (HBT) as a active device has been mounted on chip-on-board (COB) type hybrid ICs such as LNA, mixer, and VCO in RF front-end of the engine 1 board. A 6-channel digital correlator together with a real-time clock and a microprocessor interface has been realized using an Altera Flex 10K FPGA as well as ASIC technology. Navigation software controlling the correlator for GPS signal tracking, retrieval and storing a message retrieval, and position calculation has been implemented. The GPS receiver was tested using a single channel STR2770 simulator. Successful navigation message retrieval and position determination was confirmed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.77-84
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• 2007

In this parer, a wideband low-noise amplifier (LNA) has been realized in a 0.18mm CMOS technology for the applications of subsampling direct-conversion RF receivers. By exploiting the inverter-type transimpedance input stage with a 3rd-order Chebyshev matching network, the wideband LNA demonstrates the measured results of the -3dB bandwidth of 5.35GHz, the power gain (S21) of $12\sim18dB$, the noise figure (NF) of $6.9\sim10.8dB$, and the broadband input/output impedance matching of less than -10dB/-24dB within the bandwidth, respectively. The chip dissipates 32.4mW from a single 1.8V supply, and occupies the area of $0.56\times1.0mm^2$.

• ETRI Journal
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• v.38 no.4
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• pp.665-674
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• 2016

We designed and fabricated a semiconductor optical amplifier-integrated dual-mode laser (SOA-DML) as a compact and widely tunable continuous-wave terahertz (CW THz) beat source, and a pin-photodiode (pin-PD) integrated with a log-periodic planar antenna as a CW THz emitter. The SOA-DML chip consists of two distributed feedback lasers, a phase section for a tunable beat source, an amplifier, and a tapered spot-size converter for high output power and fiber-coupling efficiency. The SOA-DML module exhibits an output power of more than 15 dBm and clear four-wave mixing throughout the entire tuning range. Using integrated micro-heaters, we were able to tune the optical beat frequency from 380 GHz to 1,120 GHz. In addition, the effect of benzocyclobutene polymer in the antenna design of a pin-PD was considered. Furthermore, a dual active photodiode (PD) for high output power was designed, resulting in a 1.7-fold increase in efficiency compared with a single active PD at 220 GHz. Finally, herein we successfully show the feasibility of the CW THz system by demonstrating THz frequency-domain spectroscopy of an ${\alpha}$-lactose pellet using the modularized SOA-DML and a PD emitter.

• ETRI Journal
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• v.42 no.4
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• pp.549-561
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• 2020

We developed a 0.1-㎛ metamorphic high electron mobility transistor and fabricated a W-band monolithic microwave integrated circuit chipset with our in-house technology to verify the performance and usability of the developed technology. The DC characteristics were a drain current density of 747 mA/mm and a maximum transconductance of 1.354 S/mm; the RF characteristics were a cutoff frequency of 210 GHz and a maximum oscillation frequency of 252 GHz. A frequency multiplier was developed to increase the frequency of the input signal. The fabricated multiplier showed high output values (more than 0 dBm) in the 94 GHz-108 GHz band and achieved excellent spurious suppression. A low-noise amplifier (LNA) with a four-stage single-ended architecture using a common-source stage was also developed. This LNA achieved a gain of 20 dB in a band between 83 GHz and 110 GHz and a noise figure lower than 3.8 dB with a frequency of 94 GHz. A W-band image-rejection mixer (IRM) with an external off-chip coupler was also designed. The IRM provided a conversion gain of 13 dB-17 dB for RF frequencies of 80 GHz-110 GHz and image-rejection ratios of 17 dB-19 dB for RF frequencies of 93 GHz-100 GHz.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.3
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• pp.1-9
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• 2003

We analyze the performances of MC-CDMA and MC-DS/CDMA systems on quasi-synchronized mobile satellite return link. Quasi-synchronization is considered that chip offset between user terminals is within a few chips. Since the transmitted signals of MC-CDMA and MC-DS/CDMA systems have non-constant envelop, they are easily distorted by nonlinearity of transmit amplifier. Since the nonlinear amplifier input signal level of MC-CDMA system using Walsh code to employ frequency domain spreading is lower than that of MC-DS/CDMA system, performance of single user in MC-CDMA system is respectively 2.3dB and 1dB better than that of MC-DS/CDMA system when amplifier input backoff is 0dB and 6dB. However, since interference of MC-DS/CDMA is less than that of MC-CDMA with many subcarriers in quasi-synchronization and AWGN channel, MC-DS/CDMA system is much better than MC-CDMA system as the number of users increases.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.35-44
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• 2005

SoC(systnn-on-a-chip) requires high bandwidth system bus for performing multiple functions. Performance of the system is affected by bandwidth of the system bus. In this paper, for efficient management of the bus resource on a SoC platform, we present a latency model of the shared bus organized by multiple layers. Using the latency model, we can analyze latencies of the shared bus on a SoC. Moreover we evaluate a throughput of the bus and compare with needed throughput of the SoC platform including IPs such as MPEG or USB 2.0. And we can use the results as a criteria to find out an optimal bus architecture for the specific SoC design. For verifying accuracy of the proposed model, we compared the latencies with the simulation result from MaxSim tools. As the result of simulation, the accuracy of the IS model for a single layer and multiple layer are over $96\%\;and\;85\%$ respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.44-55
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• 2001

MAC(Multiply and ACcumulate) is the core operation of multimedia data processing. Because MAC units implemented on traditional DSP units or embedded processors have latency of three cycles and cannot operate on multiple data simultaneously, then, performances are seriously limited. Many high end general purpose microprocessors have SIMD MAC unit as a functional unit. But these high end MAC units must support pipeline structure for various operation modes and high clock frequency, which makes control logic complex and increases chip area. In this paper, a 64bit SIMD MAC unit for embedded processors is designed. It is implemented to have a latency of one clock cycle to remove pipeline control logics and a minimal area overhead for SIMD support is added to existing Booth multipliers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.11
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• pp.1349-1355
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• 2016

It should guarantee high reliability and ultra low latency communication. Additionally, it should support connection between massive devices. As one of estimated scenarios for 5G mobile communication, mobile devices and sensors using low data rate wireless communication will increase. For communication of these devices, single-carrier system can be considered. In order to satisfy these requirements, in this paper, we propose CDMA (Code Division Multiple Access) system using complex spreading and Multi-level BPSK(Binary Phase Shift Keying). The proposed system spread transmit symbol by using chip code consisted of real and imaginary number. As simulation results, we can confirm that although the proposed system has 3dB lower BER (Bit Error Rate) performance than conventional CDMA system, the proposed system can support 2 times more users in comparison with conventional CDMA system.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.4
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• pp.419-427
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• 2016

In this paper, a 64b small-area MTP memory IP is designed. A VPPL (=VPP/3) regulator and a VNN (=VNN/3) charge pump are removed since the inhibit voltages of an MTP memory cell are all 0V instead of the conventional voltages of VPP/3 and VNN/3. Also, a VPP charge pump is removed since the VPP program voltage is supplied from an external pad. Furthermore, a VNN charge pump is designed to provide its voltage of -VPP as a one-stage negative charge pump using the VPP voltage. The layout size of the designed 64b MTP memory IP with MagnaChip's $0.18{\mu}m$ BCD process is $377.585{\mu}m{\times}328.265{\mu}m$ (=0.124mm2). Its DC-DC converter related layout size is 76.4 percent smaller than its conventional counterpart.