• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.61-70
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• 2007

The density of Memory has been increased by great challenge for memory technology. Therefore, elements of memory become more smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. In addition, as the number of storage elements per chip increases, the test cost becomes more remarkable as the cost per transistor drops. Recent development in system-on-chip (SOC) technology makes it possible to incorporate large embedded memories into a chip. However, it also complicates the test process, since usually the embedded memories cannot be controlled from the external environment. Proposed design doesn't need controls from outside environment, because it integrates into memory. In general, there are a variety of memory modules in SOC, and it is not possible to test all of them with a single algorithm. Thus, the proposed scheme supports the various memory testing process. Moreover, it is able to At-Speed test in a memory module. consequently, the proposed is more efficient in terms of test cost and test data to be applied.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.31-32
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• 2010

In our previous reports [1-3], electron transport for the switching and memory devices using alkyl thiol-tethered Ru-terpyridine complex compounds with metal-insulator-metal crossbar structure has been presented. On the other hand, among organic memory devices, a memory based on the OFET is attractive because of its nondestructive readout and single transistor applications. Several attempts at nonvolatile organic memories involve electrets, which are chargeable dielectrics. However, these devices still do not sufficiently satisfy the criteria demanded in order to compete with other types of memory devices, and the electrets are generally limited to polymer materials. Until now, there is no report on nonvolatile organic electrets using nano-interfaced organic monomer layer as a dielectric material even though the use of organic monomer materials become important for the development of molecularly interfaced memory and logic elements. Furthermore, to increase a retention time for the nonvolatile organic memory device as well as to understand an intrinsic memory property, a molecular design of the organic materials is also getting important issue. In this presentation, we report on the OFET memory device built on a silicon wafer and based on films of pentacene and a SiO2 gate insulator that are separated by organic molecules which act as a gate dielectric. We proposed push-pull organic molecules (PPOM) containing triarylamine asan electron donating group (EDG), thiophene as a spacer, and malononitrile as an electron withdrawing group (EWG). The PPOM were designed to control charge transport by differences of the dihedral angles induced by a steric hindrance effect of side chainswithin the molecules. Therefore, we expect that these PPOM with potential energy barrier can save the charges which are transported to the nano-interface between the semiconductor and organic molecules used as the dielectrics. Finally, we also expect that the charges can be contributed to the memory capacity of the memory OFET device.[4]

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.103-106
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• 2012

A memory access method that data are read with different sequences with writing order is a simple but important procedure in many image compression standards, such as JPEG, MPEG1/2/4, H.264, and HEVC. For real time processing, double buffering is widely used using two block sized buffers, that accesses buffers concurrently with alternative way to read and write. In some cases like a transpose memory in 2D DCT with a simple and regular access order, a single buffering which requires only single block sized buffer can be used. This paper shows that even in complex access orders there is a regularity among updating orders within a finite turns, and suggested an effective implementation method using a single block sized buffer to process concurrent read/write operation with different access orders.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.3
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• pp.521-527
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• 2011

POWER PC series are common to the Central Processing Unit for Military Single Board Computer. Among them, G4 group, which contains the 74xx series supported by Freescale manufacturer is mainly used in the Military applications. We focus on the Interface between memory and controller. PCB stacking method, component routing, impedance matching and harsh environment for Military spec are the main constraints for implementation. Also, we developed memory as a module for the consideration of Military environments. The overall type of SBC should be designed by the form of 6U VME or 3U VME. Therefore this study suggests the electrically optimum Interface matching, Artwork technology based on the signal cross over and PCB stacking method on the harsh environment.

• Aerospace Engineering and Technology
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• v.11 no.2
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• pp.73-79
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• 2012

Because the contact time between satellite and ground station is very limited in LEO (Low Earth Orbit) satellite, all telemetry data generated on spacecraft bus are stored in a mass memory and downlinked to the ground together with real time data during the contact time. The mass memory is initialized in the first system initialization phase and the page status of each memory block is generated step by step. After the completion of the system initialization, the telemetry data are continuously stored and the stored data are played back to the ground by command. And the memory scrubbing is periodically performed for correction of single bit error which can be generated on harsh space environment. This paper introduces the mass memory operation method for telemetry processing of LEO satellite. It includes a general mass memory data structure, the methods of mass memory initialization, scrubbing, data storage and downlink, and mass memory management of primary and redundant mass memory.

• Journal of the Korean Society of Clothing and Textiles
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• v.44 no.6
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• pp.1154-1162
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• 2020

In this study, the soft textile actuator is produced for a smart wearable with the shape memory effects from linear shape memory alloys of Nickel and Titanium using the driving force through the fabrication process. The measurement model was designed to measure dynamic characteristics. The heating method, and memory shape of the linear shape memory alloy were set to measure the operating temperature. A shape memory alloy at 40.13℃, was used to heat the alloy with a power supply for the selective operation and rapid reaction speed. The required amount of current was obtained by calculating the amount of heat and (considering the prevention of overheating) set to 1.3 A. The fabrication process produced a soft textile actuator using a stitching technique for linear shape memory alloys at 0.5 mm intervals in the general fabric. The dynamic characteristics of linear shape memory alloys and actuators were measured and compared. For manufactured soft textile actuators, up to 0.8 N, twice the force of the single linear shape memory alloy, 0.38 N, and the response time was measured at 50 s.

• Journal of Internet of Things and Convergence
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• v.9 no.1
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• pp.19-24
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• 2023

Recently, with the recent rapid development of memory technology, various types of memory are developed and are used to improve processing speed in data management systems. In particular, NAND flash memory is used as a main media for storing data in memory-based storage devices because it has a nonvolatile characteristic that it can maintain data even at the power off state. However, since the recently studied memory-based storage device consists of various types of memory such as MRAM and PRAM as well as NAND flash memory, research on memory management technology is needed to improve data processing performance and efficiency of media in a storage system composed of different types of memories. In this paper, we propose a memory mapping scheme thought technique for efficiently managing data in the storage device composed of various memories for data management. The proposed idea is a method of managing different memories using a single mapping table. This method can unify the address scheme of data and reduce the search cost of data stored in different memories for data tiering.

• Journal of Broadcast Engineering
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• v.11 no.3 s.32
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• pp.320-325
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• 2006

An image is partitioned into non-overlapping $8{\times}8$ blocks fer JPEG compression. A scan order converter is placed before the JPEG encoder to provide $8{\times}8$ blocks from the pixels in raster scan order. In general, its architecture requires two line memories for storing eight lines separately to allow the concurrent memory access by both the camera and JPEG processors. Although such architecture is simple to be implemented, it can be inefficient due to too excessive memory requirement as the image resolution increases. However, no deterministic addressing equation has been developed for scan conversion. In this paper, an effective memory addressing algorithm is proposed that can be devised only by adders and subtracters to implement a scan converter based on the single line memory.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.33 no.11
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• pp.115-120
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• 2005

This paper describes the design and implementation of engineering model(EM) of Mass Memory Unit(MMU) for Science and Technology Satellite 2(STSAT-2) and the results of integration test. The use of Field-Programmable Gate Array(FPGA) instead of using private electric parts makes a miniaturization and lightweight of MMU possible. 2Gbits Synchronous Dynamic Random Access Memory(SDRAM) module for mass memory is used to store payload and satellite status data. Moreover, file system is applied to manage them easily in the ground station. RS(207,187) code improves the tolerance with respect to Single Event Upset(SEU) induced in SDRAM. The simulator is manufactured to verify receiving performance of payload data.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.1
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• pp.62-66
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• 2009

Recently developed compilers perform some optimizations in order to speed up the execution time of source program. These optimizations require the transformation of the sequence of program statements. This transformation does not give any problems in a single-threaded program. However, the transformation gives some significant errors in a multi-threaded program. State-of-the-art model checkers such as Java-Pathfinder do not consider the transformation resulted in the optimization step in a compiler since they just consider a single memory model. In this paper, we describe a new technique which is based on SMT solver. The Java Memory Model Simulator based on SMT Solver can compute all possible output of given multi-thread program within one second which, in contrast, Traditional Java Memory Model Simulator takes one minute.