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Single memory based scan converter for embedded JPEG encoder  

Park Hyun-Sang (Division of Electrical and Electronics Engineering, Kongju National University)
Publication Information
Journal of Broadcast Engineering / v.11, no.3, 2006 , pp. 320-325 More about this Journal
Abstract
An image is partitioned into non-overlapping $8{\times}8$ blocks fer JPEG compression. A scan order converter is placed before the JPEG encoder to provide $8{\times}8$ blocks from the pixels in raster scan order. In general, its architecture requires two line memories for storing eight lines separately to allow the concurrent memory access by both the camera and JPEG processors. Although such architecture is simple to be implemented, it can be inefficient due to too excessive memory requirement as the image resolution increases. However, no deterministic addressing equation has been developed for scan conversion. In this paper, an effective memory addressing algorithm is proposed that can be devised only by adders and subtracters to implement a scan converter based on the single line memory.
Keywords
JPEG; Compression; Raster scan; Block scan; ISP; SoC;
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