• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.3
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• pp.177-184
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• 2017

High performance non-volatile memory system can mitigate the gap between main memory and storage. However, no single memory devices fulfill the requirements. Non-volatile Dual In-line Memory Module (NVDIMM) consisted of DRAMs and NAND Flashes has been proposed to achieve the performance and non-volatility simultaneously. When power outage occurs, data in DRAM is backed up into NAND Flash using a small-size external energy storage such as a supercapacitor. Backup and restore operations of NVDIMM do not cooperate with the operating system in the NVDIMM standard, thus there is room to optimize its operation. This paper analysis the operation of NVDIMM and proposes a method to reduce backup and restore time. Particularly, data compression is introduced to reduce the amount of data that to be backed up and restored. The simulation results show that the proposed method reduces up to 72.6% of backup and restore time.

• Journal of Ginseng Research
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• v.20 no.1
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• pp.7-14
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• 1996

This study was performed to examine the effect of red ginseng total saponin and extract on memory in mice using one trial step-down type passive avoidance method. Red ginseng total saponins (No. 1: PD/PT ratio=1.24, No. 2: PD/PT ratio=1.47) were prepared with the different mixing ratio by using the parts of red ginseng. In single administration of total saponin No. 1 (100 mg/ kg, bw) or No. 2 (50 mg/kg, bw) increased the latency time as compared with control group but was not statistically significant. Treatment of total saponin No. 1 (50 mg/kg, bw) for 10 days produced an increase of latency time but was not statistically significant. In scopolamine-induced memory deficient mice total saponin No. 1 (50 mg/kg, bw) and No. 2 (100 mg/kg, bw) significantly improved the latency time. These results show that red ginseng total saponin may improve the memory of sco-polamine-induced memory deficient mice and have nootropic activity.

• Journal of Electrical Engineering and information Science
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• v.2 no.4
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• pp.8-13
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• 1997

This paper describes a scalable systolic synchronous memory for digital signal processing and packet switching. The systolic synchronous memory consists of the 2-D array of small memory blocks which are fully pipelined and communicated in three directions with adjacent blocks. The maximum delay of a small memory block becomes the operation speed of the chip. The array configuration is scalable for the entire memory size requested by an application. it has the initial latency of N+3 cycles with NxN array configuration. We designed an experimental 200 MHz 4Kb static RAM chip with the 4x4 array configuration of 256 SRAM blocks. It was fabricated is 0.8$\mu\textrm{m}$ twin-well single-poly double-metal CMOS technology.

• Journal of the Korean Vacuum Society
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• v.22 no.3
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• pp.144-149
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• 2013

We use Memory function to examine the thermal conductivity as a function of the temperature in single-walled carbon nanotube (SWNT). We determine the Umklapp, normal and SWNT-substrate phonon scattering rate from the computed inverse spin relaxation time. Thermal conductivity increased as the diameter increased when we assumed that the zigzag (10,0) transition was a more dominant phonon scattering than the (9,0) transition.

• Korean Journal of Materials Research
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• v.13 no.6
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• pp.352-359
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• 2003

In order to control the grain size, the spark plasma sintering technique is applied for the manufacturing of Cu-26.7Al-4.05AI(wt.%) shape memory alloy with pure Cu, Zn, and Al element powders. The sintering processes were carried out under different atmospheres. The sintered bodies were denser under Ar or Ar＋4%$H_2$gas atmosphere than under vacuum. With use of small-sized powders, a very small average grain size of 2∼3 $\mu\textrm{m}$ was obtained, but the single phase was not formed. With the large-sized powders the single austenitic phase was observed with the average grain size of $70∼72\mu\textrm{m}$. When the different size of raw powders was mixed, it is confirmed that the average grain size of the manufactured alloys was 15 $\mu\textrm{m}$ with single austenitic phase, but the distribution of grain size was not uniform.

• The Transactions of the Korea Information Processing Society
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• v.7 no.4
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• pp.1082-1091
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• 2000

In Distributed Shared Memory systems, false sharing occurs when two different data items, not shared but accessed by two different processors, are allocated to a single block and is an important factor in degrading system performance. The paper first analyzes shared memory allocation and reference patterns in parallel applications that allocate memory for shared data objects using a dynamic memory allocator. The shared objects are sequentially allocated and generally show different reference patterns. If the objects with the same size are requested successively as many times as the number of processors, each object is referenced by only a particular processor. If the objects with the same size are requested successively much more than the number of processors, two or more successive objects are referenced by only particular processors. On the basis of these analyses, we propose a memory allocation scheme which allocates each object requested by different processors to different pages and evaluate the existing memory allocation techniques for reducing false sharing faults. Our allocation scheme reduces a considerable amount of false sharing faults for some applications with a little additional memory space.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1226-1227
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• 2008

In this study, a single p-type Si nanowire - Au nanoparticles nano floating gate memory (NFGM) device is successfully fabricated and characterized their memory effects by comparison of electrical characteristics of p-type Si nanowire-based field effect transistor (FET) devices with Au nanoparticles embedded in the $Al_2O_3$ gate materials and without the Au nanoparticles. Drain current versus gate voltage ($I_{DS}-V_{GS}$) characteristics of a single p-type Si nanowire - Au nanoparticle NFGM device show counterclockwise hysteresis loops with the threshold voltage shift of ${\Delta}V_{th}$= 3.0 V. However, p-type Si nanowire based top-gate device without Au nanoparticles does not exhibit a threshold voltage shift. This behavior is ascribed to the presence of the Au nanoparticles, and is indicative of the trapping and emission of electrons in the Au nanoparticles.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.430-439
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• 2004

This paper describes a design of 8192/2048-point FFT/IFFT processor (CFFT8k2k), which performs multi-carrier modulation/demodulation in OFDM-based DVB-T receiver. Since a large size FFT requires a large buffer memory, two design techniques are considered to achieve memory-efficient implementation of 8192-point FFT/IFFT. A hybrid structure, which is composed of radix-4 single-path delay feedback (R4SDF) and radix-4 single-path delay commutator (R4SDC), reduces its memory by 20% compared to R4SDC structure. In addition, a memory reduction of about 24% is achieved by a novel two-step convergent block floating-point scaling. As a result, it requires only 57% of memory used in conventional design, reducing chip area and power consumption. The CFFT8k2k core is designed in Verilog-HDL, and has about 102,000 Bates, RAM of 292k bits, and ROM of 39k bits. Using gate-level netlist with SDF which is synthesized using a $0.25-{\um}m$ CMOS library, timing simulation show that it can safely operate with 50-MHz clock at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. The functionality of the core is fully verified by FPGA implementation, and the average SQNR of 60-㏈ is achieved.

• Journal of Space Technology and Applications
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• v.3 no.4
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• pp.333-341
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• 2023

This study aims to develop technology for testing and verifying the space radiation environment of miniature space components using the facilities of the domestic 100 MeV proton accelerator and the Space Component Test Facility at the Space Testing Center. As advancements in space development progress, high-performance satellites increasingly rely on densely integrated circuits, particularly in core components components like memory. The application of semiconductor components in essential devices such as solar panels, optical sensors, and opto-electronics is also on the rise. To apply these technologies in space, it is imperative to undergo space environment testing, with the most critical aspect being the evaluation and testing of space components in high-energy radiation environments. Therefore, the Space Testing Center at the Korea testing laboratory has developed a radiation testing device for memory components and conducted radiation impact assessment tests using it. The investigation was carried out using 100 MeV protons at a low flux level achievable at the Gyeongju Proton Accelerator. Through these tests, single event upsets observed in memory semiconductor components were confirmed.

• Biomedical Science Letters
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• v.8 no.3
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• pp.167-172
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• 2002

Effect of single administration of Polygala tenuipolia was examined on short-term memory in step through test and the intensity of the immunoreactive c-Fos protein induced by oral administration of ethanol. The acquisition of memory was significantly reduced by ethanol, and ethanol amnesia was remarkably reversed following oral administration of Polygala tenuifolia. c-Fos protein in normal rat brain was highly expressed in order of thalamus, pariental cortex, hippocampus, hypothalamus, amygdaloid and cingulate cortex. The expression of Fos protein was remarkably suppressed by single administration of ethanol. The inhibitory effect of ethanol on expression of Fos protein was reversed by single administration of Polygara tenuipolia, especially tissues of limbic areas such as amygdala, parietal cortex and CA3 of hippocampus. These results suggested that the amelioration process of Polygala tenuipolia on ethanol amnesia seems to be involve the expression of c-Fos protein in partly.