• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5B
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• pp.899-912
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• 2000

PVM provides users with a single image of high performance parallel computing machine by collecting machines distributed over a network. Low communication overhead is essential to effectively run applications on PVM based platforms. In the original PVM, three times of memory copies are required for a PVM task to send a message to a remote task, which results in performance degradation. We propose a zero-copy model using global shared memory that can be accessed by PVM tasks, PVM daemon, and network interface card(NIC). In the scheme, a task packs data into global shared memory, and notify daemon that the data is ready to be sent, then daemon routes the data to a remote task to which it is sent with no virtual data copy overhead. Experimental result reveals that the message round trip time between two machines is reduced significantly in the proposed zero-copy scheme.

• The Korea Journal of Herbology
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• v.22 no.4
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• pp.51-58
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• 2007

Objectives : Investigation of the memory and cognitive enhancing effect of HT008-1 in scopolamine induced amnesia mice. Methods : At 60 min before acquisition trials, HT008-1 (30, 100, 300 mg/kg p.o.) was administered, and 30 min later, mice were injected with scopolamin (1.0 mg/kg, i.p.). In the passive avoidance test, acquisition trials were carried out 30 min after a single scopolamine treatment. Retention trials were carried out 24h after acquisition trials. Y-maze test was carried out 30 min after a single scopolamine treatment. Spontaneous alternation behavior during an 8-min session was recorded. Inhibitory effects of HT008-1 (0.01, 0.1, 1.0 mg/ml) on AChE activity was measured. Result : HT008-1 ameliorated scopolamine-induced learning impairments and spatial cognitive function in passive avoidance and Y-maze test, respectively. Moreover HT008-1 showed a significant inhibitory effect on AChE activity. Discussion: This study presented that eMultiherb mixture HT008-1 enhanced learning memory and spatial cognitive function in scopolamine-induced amnesia mice. These results suggest that the effect of HT008-1 may be dependent on the inhibition of AChE activity.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.136-142
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• 2013

CRC features have been added to increase the reliability of the data in memory products for high-speed operation, such as DDR4. High-speed memory products in a shortage of internal timing margin increases for the CRC calculation. Because the existing CRC requires many additional circuit area and delay time. In this paper, we show that the matrix-type CRC and a new XOR/XNOR gate could be improved the circuit area and delay time. Proposed matrix-type CRC can detect all odd-bit errors and can detect even number of bit errors, except for multiples of four bits. In addition, a single error in the error correction can reduce the burden of re-transmission of data between memory products and systems due to CRC errors. In addition, the additional circuit area, compared to existing methods can be improved by 57%. The proposed XOR gate which is consists of six transistors, it can reduce the area overhead of 35% compared to the existing CRC, 50% of the gate delay can be reduced.

• The Transactions of the Korea Information Processing Society
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• v.3 no.1
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• pp.107-117
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• 1996

This paper proposes a conceptual model for distributed problem solving(DPS), where cooperation and communication among agents are based on virtual shared memory (VSM) In this model, all agents in a DPS system view all the memory in a distributed computer system as a single shared memory in which data, tasks, and results can in a distributed computer system as a single shared memory, in which data, tasks, and results can / be accessed by any of the agents. Several agents cooperatively solve a complex problem, as agents write data, intermediate results of execution, and tasks requested to other agents to VSM and other agents read or execute them. Also, in order to develop DPS systems based on the proposed conceptual model, this paper designs a DPS system development environment(DPS-VSM)using Network Linda. Thi spaper shows utility ofthe proposed model by presenting an example of simulation a VSM-based DPS system, and analyzes the model by comparing the features of DPS- VSM with some other DAI programming shells.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.5
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• pp.737-748
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• 1995

In this paper, we studyed the variables in the design of multichip memory modules with 4M$\times$1bit DRAM chips to construct high capacity and high speed memory modules. The configuration of the module was 8 bit, 16 bit, and 32 bit DRAM modules with employing 0.6 W, 70 nsec 4M$\times$1 bit DRAM chips. We optimized routing area and wiring density by performing the routing experiment with the variables of the chip allocation, module I/O terminal, the number of wiring, and the number of mounting side of the chips. The multichip module was designed to be able to accept MCM-L techiques and low cost PCB materials. The module routing experiment showed that it was an efficient way to align chip I/O terminals and module I/O terminals in parallel when mounting bare chips, and in perpendicular when mounting packaged chips, to set module I/O terminals in two sides, to use double sided substrates, and to allocate chips in a row. The efficient number of wiring layer was 4 layers when designing single sided bare chip mounting modules and 6 layers when constructing double sided bare chip mounting modules whereas the number of wiring layer was 3 layers when using single sided packaged chip mounting substrates and 5 layers when constructing double sided packaged chip mounting substrates. The most efficient configuration was to mount bare chips on doubled substrates and also to increase the number of mounting chips. The fabrication of memory multichip module showed that the modules with bare chips can be reduced to a half in volume and one third in weight comparing to the module with packaged chips. The signal propagation delay time on module substrate was reduced to 0.5-1 nsec.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.32-38
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• 2009

FTT(Fast Fourier Transform) processor is widely used in OFDM(Orthogonal Frequency Division Multiplesing) system. Because of the increased requirement of mobility and bandwidth in the OFDM system, they need large point FTT processor. Since the size of memory which stores the twiddle factor coefficients are proportional to the N of FFT size, we propose a new method by which we can reduce the size of the coefficient memory. In the proposed method, we exploit a counter and unsigned multiplier to generate the twiddle factor indices. To verify the proposed algorithm, we design TFCGs(Twiddle Factor Coefficient Generator) for 1024pint FFTs with R2SDF(Radix-2 Single-Path Delay Feedback), $R2^3SDF,\;R2^3SDF,\;R2^4SDF$ architectures. The size of ROM is reduced to 1/8N. In the case of $R2^4SDF$ architecture, the area and the power are reduced by 57.9%, 57.5% respectively.

• The KIPS Transactions:PartD
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• v.15D no.1
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• pp.99-106
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• 2008

Recently developed compilers perform some optimizations in order to speed up the execution time of source program. These optimizations require the reordering of the sequence of program statements. This reordering does not give any problems in a single-threaded program. However, the reordering gives some significant errors in a multi-threaded program. State-of-the-art model checkers such as JavaPathfinder do not consider the reordering resulted in the optimization step in a compiler since they just consider a single memory model. In this paper, we develop a new verification tool to verify Java source program based on Java Memory Model. And our tool is capable of handling the reordering in verifying Java programs. As a result, our tool finds an error in the test program which is not revealed with the traditional model checker JavaPathFinder.

• Journal of Convergence for Information Technology
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• v.9 no.8
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• pp.134-139
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• 2019

This paper describes the effect of multiple signal regeneration in quadrature digital radio frequency memory(DRFM). Single channel DRFM have good reproducibility after storing a single signal. However, when reproduced after storing multiple signals, the spurious signal is large. The quadrature DRFM consists of I and Q channels, which can greatly reduce the spurious signal. The amplitude of the spurious signal depends on the number of bits of data stored in the DRFM. In this paper, we have obtained the number of bits of signal regeneration according to the application of radio frequency memory by obtaining the size of the spurious signal according to the number of bits of the stored data of the DRFM for multiple signals. As a result of this study, 4 bits quadrature DRFM can achieve a spurious output of less than -20dB, which is used for 4 signals. Those are expected to greatly contribute to the signal analysis of electronic warfare equipment and the development of jamming device.

• The Journal of Korean society of community based occupational therapy
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• v.3 no.1
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• pp.67-75
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• 2013

Objective : The purpose of study was to visual scanning program on the effect of visual memory in stroke patients. Method : A single subject experimental research with ABA design was employed in this study. The experiment composed of 15 sessions in total: 5 sessions for baseline, 7 session for visual scanning program, and 3 sessions for the second baseline. Each session for intervention took 30 minutes daily. MVPT, CNT(visual span test, visual learning test) were used for assessment visual perception, visual memory. Result : After visual scanning program, changing faster processing time MVPT 5.5 seconds to 4.5 seconds. Also all itme raw score changes of CNT visual span test, visual learning test. Conclusion : Visual scanning program in stroke patients give a positive impact on the visual memory. To improve stroke patients' perception visual scanning program utilizing visual perception research as well as training programs for a variety of looks forward to being developed.

• Journal of the Korea Society of Computer and Information
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• v.13 no.7
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• pp.117-126
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• 2008

Recent advances in medical imaging technologies have enabled the high-resolution data acquisition. Therefore visualization of such large data set on standard graphics hardware became a popular research theme. Among many visualization techniques, we focused on bricking method which divided the entire volume into smaller bricks and rendered them in order. Since it switches bet\W8n bricks on main memory and bricks on GPU memory on the fly, to achieve better performance, the number of these memory swapping conditions has to be minimized. And, because the original bricking algorithm was designed for regular volume data such as CT and MR, when applying the algorithm to ultrasound volume data which is based on the toroidal coordinate space, it revealed some performance degradation. In some areas near bricks' boundaries, an orthogonal viewing ray intersects the single brick twice, and it consequently makes a single brick memory to be uploaded onto GPU twice in a single frame. To avoid this redundancy, we divided the volume into bricks allowing overlapping between the bricks. In this paper, we suggest the formula to determine an appropriate size of these shared area between the bricks. Using our formula, we could minimize the memory bandwidth. and, at the same time, we could achieve better rendering performance.