• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 2003년도 ISIS 2003
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• pp.640-643
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• 2003

A Walsh function based associative memory is capable of storing m patterns in a single pattern storage space with Walsh encoding of each pattern. Furthermore, each stored pattern can be matched against the stored patterns extremely fast using algorithmic parallel processing. As such, this special type of memory is ideal for real-time processing of large scale information. However this incredible efficiency generates large amount of crosstalk between stored patterns that incurs mis-recognition. This crosstalk is a function of the set of different sequencies [number of zero crossings] of the Walsh function associated with each pattern to be stored. This sequency set is thus optimized in this paper to minimize mis-recognition, as well as to maximize memory saying. In this paper, this Walsh memory has been applied to the problem of face recognition, where PCA is applied to dimensionality reduction. The maximum Walsh spectral component and genetic algorithm (GA) are applied to determine the optimal Walsh function set to be associated with the data to be stored. The experimental results indicate that the proposed methods provide a novel and robust technology to achieve an error-free, real-time, and memory-saving recognition of large scale patterns.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권1호
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• pp.27-31
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• 2008

We have studied nonvolatile memory properties of MOSFETs with double-stacked Si nanoclusters in the oxide-gate stacks. We formed Si nanoclusters of a uniform size distribution on a 5 nm-thick tunneling oxide layer, followed by a 10 nm-thick intermediate oxide and a second layer of Si nanoclusters by using LPCVD system. We then investigated the memory characteristics of the MOSFET and observed that the charge retention time of a double-stacked Si nanocluster MOSFET was longer than that of a single-layer device. We also found that the double-stacked Si nanocluster MOSFET is suitable for use as a dual-bit memory.

• 생약학회지
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• 제41권3호
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• pp.196-203
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• 2010

Black sesame (Sesami semen nigrum) has been used to treat dizziness, earnoise, constipation in the traditional Chinese medicine. In the present study, we assessed memory enhancing properties of 70% ethanolic extract of black sesame (EBS70) and its ameliorating activities on learning and memory impairments induced by scopolamine. Drug-induced amnesia was made by scopolamine treatment (1 mg/kg, i.p.). Single EBS70 (200 mg/kg, p.o.) administration significantly enhanced cognitive function and attenuated scopolamine-induced cognitive impairments as determined by the passive avoidance and Y-maze tasks (P<0.05) and also reduced escape-latency on the Morris water maze task (P<0.05). In addition, EBS70 increased BDNF expression in hippocampus 4 h after its administration (P<0.05). These results suggest that EBS70 enhances learning and memory in normal state and attenuates amnesic state caused by cholinergic dysfunction.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권1호
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• pp.40-49
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• 2001

We have developed a repeatable process of forming uniform, small-size and high-density self-assembled Si nano-crystals. The Si nano-crystals were fabricated in a conventional LPCVD (low pressure chemical vapor deposition) reactor at $620^{\circ}c$ for 15 sec. The nano-crystals were spherical shaped with about 4.5 nm in diameter and density of $5{\times}l0^{11}/$\textrm{cm}^2$. More uniform dots were fabricated on nitride film than on oxide film. To take advantage of the above-mentioned characteristics of nitride film while keeping the high interface quality between the tunneling dielectrics and the Si substrate, nitride-oxide tunneling dielectrics is proposed in n-channel device. For the first time, the single electron effect at room temperature, which shows a saturation of threshold voltage in a range of gate voltages with a periodicity of ${\Delta}Ｖ_{GS}\;{\approx}\;1.7{\;}V$, corresponding to single and multiple electron storage is reported. The feasibility of p-channel nano-crystal memory with thin oxide in direct tunneling regime is demonstrated. The programming mechanisms of p-channel nano-crystal memory were investigated by charge separation technique. For small gate programming voltage, hole tunneling component from inversion layer is dominant. However, valence band electron tunneling component from the valence band in the nano-crystal becomes dominant for large gate voltage. Finally, the comparison of retention between programmed holes and electrons shows that holes have longer retention time.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.222.2-222.2
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• 2015

A $Ge_2Sb_2Te_5$ nanowire (GST NW) phase change memory device is investigated with Joule heating electrodes. GST is the most promising phase change materials, thus has been studied for decades but atomic structure transition in the phase-change area of single crystalline phase-change material has not been clearly investigated. We fabricated a phase change memory (PCM) device consisting of GST NWs connected with WN electrodes. The GST NW has switching performance with the reset/set resistance ratio above $10^3$. We directly observed the changes in atomic structure between the ordered hexagonal close packed (HCP) structure and disordered amorphous phase of a reset-stop GST NW with cross-sectional STEM analysis. Amorphous areas are detected at the center of NW and side areas adjacent to heating electrodes. Direct imaging of phase change area verified the atomic structure transition from the migration and disordering of Ge and Sb atoms. Even with the repeated phase transitions, periodic arrangement of Te atoms is not significantly changed, thus acting as a template for recrystallization. This result provides a novel understanding on the phase-change mechanism in single crystalline phase-change materials.

• IEIE Transactions on Smart Processing and Computing
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• 제3권1호
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• pp.1-9
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• 2014

This paper proposes a low-latency Sample Adaptive Offset filter (SAO) architecture and its Single Instruction Multiple Data (SIMD) optimization scheme to achieve fast High Efficiency Video Coding (HEVC) decoding in a multi-core environment. According to the HEVC standard and its Test Model (HM), SAO operation is performed only at the picture level. Most realtime decoders, however, execute their sub-modules on a Coding Tree Unit (CTU) basis to reduce the latency and memory bandwidth. The proposed low-latency SAO architecture has the following advantages over picture-based SAO: 1) significantly less memory requirements, and 2) low-latency property enabling efficient pipelined multi-core decoding. In addition, SIMD optimization of SAO filtering can reduce the SAO filtering time significantly. The simulation results showed that the proposed low-latency SAO architecture with significantly less memory usage, produces a similar decoding time as a picture-based SAO in single-core decoding. Furthermore, the SIMD optimization scheme reduces the SAO filtering time by approximately 509% and increases the total decoding speed by approximately 7% compared to the existing look-up table approach of HM.

• 디지털콘텐츠학회 논문지
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• 제18권7호
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• pp.1451-1456
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• 2017

본 연구에서는 형상기억합금(SMA)을 응용한 스마트 액추에이터의 효율적 제어를 위한 통합 액추에이터-제어기 시스템 설계를 논의한다. 이를 위하여 두 개의 스마트 SMA 액추에이터 유닛과 함께 제어를 위한 싱글 칩 마이크로프로세서, 액추에이터 드라이버, 센서를 통합한 새로운 액추에이터-제어기 모듈을 설계하고 제작하였다. 제안된 시스템에서는 피드백 제어를 위해 모듈의 회전을 측정하는 6축 모션센서 칩과 SMA의 저항을 측정하는 회로를 포함한다. 실험을 통하여 액추에이터의 구동과 센서 신호와 통신을 확인하였고 이를 통하여 실제 액추에이터-제어기 시스템의 작동을 확인하였다.

• 한국전기전자재료학회논문지
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• 제15권10호
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• pp.831-837
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• 2002

Scaled SONOS transistors have been fabricated by 0.35$\mu\textrm{m}$ CMOS standard logic process. The thickness of stacked ONO(blocking oxide, memory nitride, tunnel oxide) gate insulators measured by TEM are 2.5 nm, 4.0 nm and 2.4 nm, respectively. The SONOS memories have shown low programming voltages of ${\pm}$8.5 V and long-term retention of 10-year Even after 2 ${\times}$ 10$\^$5/ program/erase cycles, the leakage current of unselected transistor in the erased state was low enough that there was no error in read operation and we could distinguish the programmed state from the erased states precisely The tight distribution of the threshold voltages in the programmed and the erased states could remove complex verifying process caused by over-erase in floating gate flash memory, which is one of the main advantages of the charge-trap type devices. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ cycles can be realized by the programming method for a flash-erased type EEPROM.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.54-57
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• 2002

In this study, a new programming method, to minimize the generation of Si-SiO$_2$ interface traps of scaled SONOS flash memory as a function of number of program/erase cycles has been proposed. In the proposed programming method, power supply voltage is applied to the gate, forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim (MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and drain are open. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ prograss/erase cycles can be realized by the proposed programming method. The asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics of scaled SONOS devices because electrical stress applied to the Si-SiO$_2$ interface is reduced by short programming time.

• 정보저장시스템학회논문집
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• 제3권2호
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• pp.94-112
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• 2007

Nano-sized inverted domain dots in ferroelectric materials have potential application in ultrahigh-density rewritable data storage systems. Herein, a data storage system is presented based on scanning non-linear dielectric microscopy and a thin film of ferroelectric single-crystal lithium tantalite. Through domain engineering, we succeeded to form an smallest artificial nano-domain single dot of 5.1 nm in diameter and artificial nano-domain dot-array with a memory density of 10.1 Tbit/$inch^2$ and a bit spacing of 8.0 nm, representing the highest memory density for rewritable data storage reported to date. Sub-nanosecond (500psec) domain switching speed also has been achieved. Next, long term retention characteristic of data with inverted domain dots is investigated by conducting heat treatment test. Obtained life time of inverted dot with the radius of 50nm was 16.9 years at $80^{\circ}C$. Finally, actual information storage with low bit error and high memory density was performed. A bit error ratio of less than $1\times10^{-4}$ was achieved at an areal density of 258 Gbit/inch2. Moreover, actual information storage is demonstrated at a density of 1 Tbit/$inch^2$.