• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.4
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• pp.292-297
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• 2003

We fabricated a single crystal silicon thin film transistor for active matrix organic light emitting displays(AMOLEDs) using silicon on insulator wafer (SOI wafer). Poly crystal silicon thin film transistor(poly-Si TFT) Is actively researched and developed nowsdays for a pixel switching devices of AMOLEDs. However, poly-Si TFT has some disadvantages such as high off-state leakage currents and low field-effect mobility due to a trap of grain boundary in active channel. While single crystal silicon TFT has many advantages such as high field effect mobility, low off-state leakage currents, low power consumption because of the low threshold voltage and simultaneous integration of driving ICs on a substrate. In our experiment, we compared the property of poly-Si TFT with that of SOI TFT. Poly-Si TFT exhibited a field effect mobility of 34 $\textrm{cm}^2$/Vs, an off-state leakage current of about l${\times}$10$\^$-9/ A at the gate voltage of 10 V, a subthreshold slope of 0.5 V/dec and on/off ratio of 10$\^$-4/, a threshold voltage of 7.8 V. Otherwise, single crystal silicon TFT on SOI wafer exhibited a field effect mobility of 750 $\textrm{cm}^2$/Vs, an off-state leakage current of about 1${\times}$10$\^$-10/ A at the gate voltage of 10 V, a subthreshold slope of 0.59 V/dec and on/off ratio of 10$\^$7/, a threshold voltage of 6.75 V. So, we observed that the properties of single crystal silicon TFT using SOI wafer are better than those of Poly Si TFT. For the pixel driver in AMOLEDs, the best suitable pixel driver is single crystal silicon TFT using SOI wafer.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.20 no.4
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• pp.395-400
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• 2011

Scanning Probe Lithography is a method to localized oxidation on single crystal silicon wafer surface. This study demonstrates nanometer scale non contact lithography process on (100) silicon (p-type) wafer surface using AFM(Atomic force microscope) apparatuses and pulse controlling methods. AFM-based experimental apparatuses are connected the DC pulse generator that supplies ultra short pulses between conductive tip and single crystal silicon wafer surface maintaining constant humidity during processes. Then ultra short pulse durations are controlled according to various experimental conditions. Non contact lithography of using ultra short pulse induces electrochemical reaction between micro-scale tip and silicon wafer surface. Various growths of oxides can be created by ultra short pulse non contact lithography modification according to various pulse durations and applied constant humidity environment.

• Macromolecular Research
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• v.11 no.6
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• pp.511-513
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• 2003

Hydroxyl groups were introduced onto the surface of a silicon wafer by O$_2$ plasma treatment. Poly(l-lactide) (1-PLA) was attached onto the surface-modified silicon wafer by the ring-opening polymerization of l-lactide using the hydroxyl group as an initiator. Lamellar single crystals of 1-PLA were grown directly on the 1-PLA-attached silicon wafer from a 0.025% solution in acetonitrile at 5$^{\circ}C$. A well-separated, lozenge-shaped, monolayered lamellar single crystal was prepared because the 1-PLA-attached silicon wafer acts as an initial nucleus.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.26 no.5
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• pp.171-174
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• 2016

The diamond wire sawing method to produce silicon wafers for the photovoltaic application is still a new and highly investigated wafering technology. This technology, featured as the higher productivity, lower wear of the wire, and easier recycling of the coolant, is expected to become the mainstream technique for slicing the silicon crystals. However, the saw marks on the wafer surface have to be investigated and improved. This paper discusses the removal of saw marks on diamond wire-sawn single crystalline silicon wafer. With a pretreatment step using tetramethyl ammonium hydroxide ($(CH_3)_4NOH$, TMAH) and conventional texturing process with KOH solution (1 % KOH, 8 % IPA, and DI water), the saw marks on the surface of the diamond wire-sawn silicon wafers can be effectively removed and they are invisible to naked eyes completely.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1103-1107
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• 2005

Single-crystal silicon thin films on glass (SOG) and on fused-quartz (SOQ) were prepared using wafer bonding and hydrogen-induced layer transfer. Thinfilm transistors (TFTs) were subsequently fabricated. The high-temperature processed SOQ TFTs show better device performance than the low-temperature processed SOG TFTs. Tensile and compressive strain was measured respectively on SOQ and SOG. Consistent with the tensile strain, enhanced electron effective mobility was measured on the SOQ TFTs.

• Journal of Power System Engineering
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• v.5 no.4
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• pp.11-17
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• 2001

Micronization of sensor is a trend of the silicon sensor development with regard to a piezoresistive silicon pressure sensor, the size of the pressure sensor diaphragm have become smaller year by year, and a microaccelerometer with a size less than $200{\sim}300{\mu}m$ has been realized, In this paper, we study some of the bonding processes of SCS(single crystal silicon) insulator wafer for the microaccelerometer. and their subsequent processes which might affect thermal loads. The finite element method(FEM) has been a standard numerical modeling technique extensively utilized in micro structural engineering discipline for design of SCS insulator wafers. Successful temperature distribution analysis and design of the SCS insulator wafers based on the tunneling current concept using microaccelerometer depend on the knowledge about normal mechanical properties of the SCS and $SiO_2$ layer and their control through manufacturing processes.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.20 no.10
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• pp.3113-3125
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• 1996

The objective of this study is to develop novel method named mechanical and chemical machining technique, which is capable of producing three dimensional patterns of few micrometers in dimension on a silicon wafer without the use of a mask. The strategy is to impart mechanical energy along the path of the pattern to be fabricated on a single crystal silicon by way on introdusing frictional interaction under controlled conditions. Then, the surface is preferentially etched to reveal the areas that have been mechanically energized. Upon completion of the etching process, the three dimensional pattern is produced on the silicon surface. Experiments have been conducted to identify the optimal tool material, geometery, as well as fabrication condition. The new technique introduced in this paper is significantly simpler than the conventional method which require sophisticated equipment and much time.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.12 no.3
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• pp.120-125
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• 2002

Si-wafers for solar cells were cast in a size of $50{\times}46{\times}0.5{\textrm}{mm}^3$ by vacuum casting method. The graphite mold coated by BN powder, which was to prevent the reaction of carbon with the molten silicon, was used. Without coating, the wetting and reaction of Si melt to graphite mold was very severe. In the case of BN coating, SiC was formed in the shape of tiny islands at the surface of Si wafer by the reaction between Si-melt and carbon of the graphite mold on the high temperature. The grain size was about 1 mm. The efficiency of Si solar cell was lower than that of Si solar cell fabricated on commercial single and poly crystalline Si wafer. The reason of low efficiency was discussed.

• Journal of the Korean Ceramic Society
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• v.28 no.6
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• pp.495-501
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• 1991

This study is intended to make defect-free region, denuded zone at the silicon wafer surface for semiconductor device substrates. In this experiment, initial oxygen concentration of starting material CZ-grown silicon wafer, various heat treatment combinations, denuding ambient and the amounts of oxygen reduction were measured, and then denuded zone (DZ) formation and depth were investigated. In Low/High anneal (DZ formation could be achieved), the optimum temperature for Low anneal was 700$^{\circ}C$∼750$^{\circ}C$. In case of High anneal, with the time increased, DZ depth was increased at 1000$^{\circ}C$, 1150$^{\circ}C$ respectively, but on the contrary, DZ depth was decreased at low temperature 900$^{\circ}C$. As well, out-diffusion time below 2 hours was unsuitable for effective Gettering technique even though the temperature was high, and DZ formation could be achieved when initial oxygen concentration was only above 14 ppm in silicon wafer.

• Journal of the Korean Society for Nondestructive Testing
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• v.36 no.1
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• pp.1-8
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• 2016

Single crystalline silicon wafers having (100), (110), and (111) directions are employed as specimens for obtaining slowness profiles. Leaky Lamb waves (LLW) from immersed wafers were detected by varying the incident angles of the specimens and rotating the specimens. From an analysis of LLW signals for different propagation directions and phase velocities of each specimen, slowness profiles were obtained, which showed a unique symmetry with different symmetric axes. Slowness profiles were compared with elastic moduli of each wafer. They showed the same symmetries as crystal structures. In addition, slowness profiles showed expected patterns and values that can be inferred from elastic moduli. This implies that slowness profiles can be used to examine crystal structures of anisotropic solids.